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| ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C SST55LD019A/B/CHigh-Performance ATA Flash Disk Controller Data Sheet FEATURES: * Industry Standard ATA/IDE Bus Interface - Host Interface: 8- or 16-bit access - Supports up to PIO Mode-4 - Supports up to Multi-word DMA Mode-2 * Interface for standard NAND Flash Media - Flash Media Interface: 8-bit or 16-bit access - Supports up to 8 flash media devices directly - Supports up to 64 flash media devices with external decoding logic - Supports Single-Level Cell (SLC) flash media - 512 Byte and 2 KByte program page size * Low power, 3.3V core operation * 5.0V or 3.3V host interface through VDDQ pins * Low current operation: - Active mode: 25 mA/35 mA (3.3V/5.0V) (typical) - Sleep mode: 40 A/50 A (3.3V/5.0V) (typical) * Power Management Unit - Immediate disabling of unused circuitry * Expanded Data Protection - WP_PD# pin configurable by firmware for prevention of data overwrites - Added data security through user-selectable protection zones * 20-byte Unique ID for Enhanced Security - Factory Pre-programmed 10-byte Unique ID - User-Programmable 10-byte ID * Integrated Voltage Detector - Industrial Controller requires external POR# signal * Pre-programmed Embedded Firmware - Performs self-initialization on first system Power-on - Executes industry standard ATA/IDE commands - Implements dynamic wear-leveling algorithms to substantially increase the longevity of flash media - Embedded Flash File System - Built-in ECC corrects up to 3 random 12-bit symbols of error per 512-byte sector * Internal or External System Clock Option * Multi-tasking Technology enables Fast Sustained Write Performance (Host to Flash) - SST55LD019A supports up to 6 MB/sec - SST55LD019B/C support up to 10MB/sec * Fast Sustained Read Performance (Flash to Host) - Up to 10 MB/sec * Automatic Recognition and Initialization of Flash Media Devices - Seamless integration into a standard SMT manufacturing process - 5 sec. (typical) for flash drive recognition and setup * Commercial and Industrial Temperature Ranges - 0C to 70C for commercial operation - -40C to +85C for industrial operation * Packages Available - 100-lead TQFP - 16mm x 16mm - 84-ball TFBGA - 9mm x 9mm - 85-ball VFBGA - 6mm x 6mm * All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION SST's ATA Flash Disk Controller is the heart of a high-performance, flash media-based data storage system. The ATA Flash Disk Controller recognizes the control, address, and data signals on the ATA/IDE bus and translates them into memory accesses to the standard NAND-type flash media. The SST55LD019A/B/C device supports Single Level Cell (SLC) flash media. This technology suits solid state mass storage applications offering new, expanded functionality while enabling smaller, lighter designs with lower power consumption. The ATA/IDE interface is widely used in such products as portable and desktop computers, digital cameras, music players, handheld data collection scanners, PDAs, handy terminals, personal communicators, audio recorders, monitoring devices, and set-top boxes. SST's ATA Flash Disk Controller supports standard ATA/IDE protocol with up to PIO Mode-4 and Multi-word DMA Mode-2 interface. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 1 Utilizing SST's proprietary SuperFlash memory technology, the ATA Flash Disk Controller is factory pre-programmed with an embedded flash file system which, upon initial Power-on, recognizes the attached flash media devices, sets up a bad block table, executes all necessary handshaking routines for flash media support, and, finally, performs the low-level format. This process typically takes about 3 sec + 0.5 sec/GByte of drive capacity, allowing a 2 GByte flash drive to be fully initialized in about 4 seconds. This technology enables a very fast, completely seamless integration of flash drives into an embedded design. For added manufacturing flexibility, system debug, re-initialization, and user customization can be accomplished either through the ATA/IDE interface, for ATA Disk Module or flash drive products, or through the Serial Communication Interface (SCI), for fully embedded ATA Flash Disk Con- The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. Some content is reproduced from the CompactFlash Specification (2.0) by permission of the CompactFlash Association. Other content is reproduced from the ATA/ATAPI-6 (T13/1410D revision 3b) specification by permission of the National Committee for Information Technology Standards. These specifications are subject to change without notice. ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet troller designs. The SST55LD019A/B/C high-performance ATA Flash Disk Controller offers sustained read and write performance up to 10.0 MB/sec. The SST55LD019A controller is to be used when the random access performance needs to be maximized. The SST55LD019B controller is to be used when the sequential access performance needs to be maximized. The SST55LD019C controller is to be used when the flash drive capacity and sequential access performance need to be maximized. The SST55LD019A/B/C can directly support up to 8 flash media devices or, through simple decoding logic, can support up to 64 flash media devices. Users can select either an internal or external system clock option for optimal performance vs. the supply current. The SST55LD019A/B/C offers added security protection for confidential information stored in the flash media. It allows up to four protection zones which can be set by the user to be Read-only or Hidden (Read-disabled). The ATA Flash Disk Controller can access the data within the protected zones through a password-protected command. The controller also provides a WP_PD# pin to protect critical information stored in the flash media from unauthorized overwrites. The ATA Flash Disk Controller comes pre-programmed with a 10-byte unique serial ID. For even greater system security, the user has the option of programming an additional 10 Bytes of ID space to create a unique, 20-byte ID. The ATA Flash Disk Controller comes packaged in an industry-standard, 100-lead TQFP package, an 84-ball TFBGA package, or a 85-ball VFBGA package for easy integration into an SMT manufacturing process. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 2 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet TABLE OF CONTENTS PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 LIST OF TABLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.0 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 Performance-optimized ATA Flash Disk Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.0 FUNCTIONAL BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.0 PIN ASSIGNMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.0 CAPACITY SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 Functional Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.0 MANUFACTURING SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 ATA/IDE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 Serial Communication Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.0 EXTERNAL CLOCK INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.0 SECURITY FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.0 CONFIGURABLE WRITE PROTECT/POWER-DOWN MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.1 Write Protect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.2 Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9.0 POWER-ON AND BROWN-OUT RESET CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10.0 I/O TRANSFER FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11.0 SOFTWARE INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 11.1 ATA Flash Disk Controller Drive Register Set Definitions and Protocol. . . . . . . . . . . . . . . . . . . . . . . . 21 11.2 ATA Flash Disk Controller Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 12.0 ELECTRICAL SPECIFICATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12.1 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.2 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 13.0 APPENDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 13.1 Differences between SST's ATA Flash Disk Controller and ATA/ATAPI-5 Specifications. . . . . . . . . . 75 14.0 PRODUCT ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 15.0 PACKAGING DIAGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 3 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet LIST OF FIGURES FIGURE 2-1: ATA Flash Disk Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FIGURE 3-1: Pin Assignments for 100-lead TQFP (TQW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 FIGURE 3-2: Pin Assignments for 84-ball TFBGA (BW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 FIGURE 3-3: Pin Assignments for 85-ball VFBGA (MVW) ..................................... 9 FIGURE 9-1: Power-on and Brown-out Reset Timing (Commercial Temperature) . . . . . . . . . . . . . . . . . . . 18 FIGURE 9-2: Power-on and Brown-out Reset Timing (Industrial Temperature) . . . . . . . . . . . . . . . . . . . . . 18 FIGURE 12-1: AC Input/Output Reference Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 FIGURE 12-2: Host Side Interface I/O Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 FIGURE 12-3: Host Side Interface I/O Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 FIGURE 12-4: Initiating a Multi-word DMA Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 FIGURE 12-5: Sustaining a Multi-word DMA Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 FIGURE 12-6: Device Terminates a Multi-word DMA Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 FIGURE 12-7: Host Terminates a Multi-word DMA Data Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 FIGURE 12-8: Media Command Latch Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 FIGURE 12-9: Media Address Latch Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 FIGURE 12-10: Media Data Loading Latch Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 FIGURE 12-11: Media Data Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 FIGURE 15-1: 100-lead Thin Quad Flat Pack (TQFP) SST Package Code: TQW . . . . . . . . . . . . . . . . . . . 76 FIGURE 15-2: 85-ball Very-Thin, Fine-Pitch, Ball Grid Array (VFBGA) SST Package Code: MVW . . . . . . 77 FIGURE 15-3: 84-ball Thin, Fine-pitch, Ball Grid Array (TFBGA) SST Package Code: BW . . . . . . . . . . . . 78 (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 4 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet LIST OF TABLES TABLE 3-1: Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 TABLE 4-1: Default ATA Flash Drive Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TABLE 4-2: Functional Specification of SST55LD019A/B/C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TABLE 9-1: Power-on and Brown-out Reset Timing (Commercial Temperature) . . . . . . . . . . . . . . . . . . . 18 TABLE 9-2: Power-on and Brown-out Reset Timing (Industrial Temperature) . . . . . . . . . . . . . . . . . . . . . 18 TABLE 10-1: I/O Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 TABLE 11-1: Task File Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 TABLE 11-2: ATA Flash Disk Controller Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 TABLE 11-3: Diagnostic Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 TABLE 11-4: Identify-Drive Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 TABLE 11-5: Extended Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 TABLE 11-6: Security Password Data Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 TABLE 11-7: Security Password Data Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 TABLE 11-8: Identifier and Security Level Bit Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 TABLE 11-9: Features Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 TABLE 11-10: Advanced Power Management Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 TABLE 11-11: Transfer Mode Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 TABLE 11-12: Set-Max Features register values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 TABLE 11-13: Set-Max-Set-Password Data Content. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 TABLE 11-14: Translate Sector Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 TABLE 11-15: Error and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 TABLE 12-1: Absolute Maximum Power Pin Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 TABLE 12-2: Recommended System Power-on Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 TABLE 12-3: Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 TABLE 12-4: Reliability Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 TABLE 12-5: DC Characteristics for Media Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 TABLE 12-6: DC Characteristics for Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 TABLE 12-7: Host Side Interface I/O Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 TABLE 12-8: Host Side Interface I/O Write Timing Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 TABLE 12-9: Multi-word DMA Timing Parameters - Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 TABLE 12-10: SST55LD019A/B/C Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 TABLE 15-1: Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 5 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 1.0 GENERAL DESCRIPTION The ATA Flash Disk Controller contains a microcontroller and embedded flash file system integrated in TQFP and TFBGA packages. Refer to Figure 2-1 for the ATA Flash Disk Controller block diagram. The controller interfaces with the host system allowing data to be written to and read from the flash media. 1.1.5 Embedded Flash File System The embedded flash file system is an integral part of the ATA Flash Disk Controller. It contains MCU firmware that performs the following tasks: 1. Translates host side signals into flash media writes and reads. 2. Provides dynamic flash media wear leveling to spread the flash writes across all unused memory address space to increase the longevity of flash media. 3. Keeps track of data file structures. 4. Manages system security for the selected protection zones. 1.1.6 Error Correction Code (ECC) The ATA Flash Disk Controller utilizes 72-bit ReedSolomon Error Detection Code (EDC) and Error Correction Code (ECC), which provides the following error immunity for each 512-byte block of data: 1. Corrects up to three random 12-bit symbol errors. 2. Corrects single bursts up to 25 bits. 3. Detects single bursts up to 61 bits and double bursts up to 15 bits. 4. Detects up to six random 12-bit symbol errors. 1.1.7 Serial Communication Interface (SCI) The Serial Communication Interface (SCI) is designed to enable the user to restart the self-initialization process and to customize the drive identification information. 1.1.8 Multi-tasking Interface The multi-tasking interface enables fast, sustained write performance by allowing concurrent Read, Program, and Erase operations to multiple flash media devices. 1.1 Performance-optimized ATA Flash Disk Controller The heart of the flash drive is the ATA Flash Disk Controller which translates standard ATA signals into flash media data and control signals. The following components contribute to the ATA Flash Disk Controller's operation. 1.1.1 Microcontroller Unit (MCU) The MCU translates ATA/IDE commands into data and control signals required for flash media operation. 1.1.2 Internal Direct Memory Access (DMA) The ATA Flash Disk Controller uses internal DMA allowing instant data transfer from buffer to flash media. This implementation eliminates microcontroller overhead associated with the traditional, firmware-based approach, thereby increasing the data transfer rate. 1.1.3 Power Management Unit (PMU) The power management unit controls the power consumption of the ATA Flash Disk Controller. The PMU dramatically reduces the power consumption of the ATA Flash Disk Controller by putting the part of the circuitry that is not in operation into sleep mode. 1.1.4 SRAM Buffer A key contributor to the ATA Flash Disk Controller performance is an SRAM buffer. The buffer optimizes the host's data transfer to and from the flash media. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 6 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 2.0 FUNCTIONAL BLOCKS ATA Flash Disk Controller Embedded Flash File System SRAM Buffer MCU NAND Flash Media Multi-tasking Interface HOST ATA/IDE BUS ECC Internal DMA PMU SCI 1241 B1.1 FIGURE 2-1: ATA Flash Disk Controller Block Diagram (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 7 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 3.0 PIN ASSIGNMENTS The signal/pin assignments are listed in Table 3-1. Low active signals have a "#" suffix. Pin types are Input, Output, or Input/Output. Signals whose source is the host are designated as inputs while signals that the ATA Flash Disk Controller sources are outputs. The ATA Flash Disk Controller functions in ATA mode, which is compatible with IDE hard disk drives. RESET# VSS (IO) D7 D6 D5 D4 VDDQ (IO) D3 D2 D1 D0 VSS (IO) TIE_DN INPACK/DMARQ DNU DNU DNU DNU IORD# DMACK INTRQ A1 A0 CS1FX# VSS (Core) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 EXTCLKIN EXTCLKOUT VSS (IO) FWP# FWE# FCE5# FALE FCE4# FCLE FCE6# VSS (IO) FCE3# FCE2# VDD (IO) FCE0# DNU FRE# DNU FRDYbsy# DNU FCE1# SCIDOUT SCIDIN SCICLK VDD (Core) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100-lead TQFP Top View 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DASP# VSS (IO) D8 D9 D10 D11 VDDQ (IO) D12 D13 D14 D15 VSS (IO) DNU WP_PD# DNU DNU DNU DNU IOWR# CSEL IOCS16# PDIAG# A2 CS2FX# VSS (Core) 1241 100-tqfp P1.0 FIGURE 3-1: Pin Assignments for 100-lead TQFP (TQW) (c)2006 Silicon Storage Technology, Inc. FCE7#/INTCLKEN VSS (IO) FAD0 FAD8 FAD1 FAD9 FAD2 FAD10 FAD3 FAD11 VSS (IO) DNU VDD (IO) FAD4 FAD12 FAD5 FAD13 FAD6 FAD14 FAD7 FAD15 DNU DNU DNU POR# 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note: DNU means Do Not Use, must be left unconnected. S71241-04-000 12/06 8 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet TOP VIEW (balls facing down) 10 DASP# D9 D11 D10 D8 D14 D13 D12 DNU WP_PD# D15 DNU DNU DNU DNU CSEL 9 SCIDOUT VDD(Core) SCICLK IOWR# PDIAG# CS3FX# IOCS16# A2 FAD7 FAD6 FAD12 FAD3 FAD9 FAD8 FAD15 FAD14 FAD5 FAD4 VDD(IO) FAD10 FAD1 1241 84-tfbga P2.2 1241 85-vfbga MW P1.2 8 FRDYbsy# FCE1# SCIDIN 7 FCE0# FRE# FCE6# FALE FWP# FCE2# VSS(IO) FCLE FCE5# D6 D7 D3 D1 D4 D2 D0 TIE_DN DMARQ DNU DNU DNU DNU IORD# VSS(IO) A1 VSS(Core) POR# FAD13 FAD11 FAD2 FAD0 6 FCE3# 5 FCE4# 4 FWE# 3 EXTCLKOUTEXTCLKIN 2 RESET# D5 VDDQ(IO) DMACK CS1FX# INTRQ A0 1 FCE7# /INTCLKEN A FIGURE B C D E F G H J K 3-2: Pin Assignments for 84-ball TFBGA (BW) TOP VIEW (balls facing down) 10 VSS VSS CS1FX# INTRQ VSS D1 VDDQ D6 VSS RESET# 9 FAD0 FAD8 Note A1 IORD# D0 D3 D5 D7 EXTCLKOUT 8 FAD1 FAD9 FAD2 A0 DMACK# DMARQ D2 D4 EXTCLKIN VSS 7 FAD10 FAD3 FAD11 FWP# FWE# FCE5# 6 VSS VDD FAD4 FALE FCE4# FCLE 5 FAD12 FAD5 FAD13 FCE6# FCE3# VSS 4 FAD6 FAD14 FAD7 VSS FCE2# FCE0# VDD 3 FAD15 POR# CSEL D15 D13 D11 D8 FRE# FRDYbsy# FCE1# 2 VSS A2 IOCS16# WP_PD# D14 D12 D9 DASP# SCIDOUT SCIDIN 1 VSS CS3FX# PDIAG# IOWR# VSS VDDQ D10 VSS VDD SCICLK A FIGURE B C D E F G H J K Note: C9 = FCE7#/IntClken 3-3: Pin Assignments for 85-ball VFBGA (MVW) S71241-04-000 12/06 (c)2006 Silicon Storage Technology, Inc. 9 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet TABLE 3-1: Pin Assignments (1 of 4) Pin No. Symbol A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DMACK DMARQ CS1FX# CS3FX# CSEL 100-TQFP 85VFBGA 84TFBGA Pin Type I/O Type1 Name and Functions Host Side Interface 53 22 23 65 66 67 68 70 71 72 73 3 4 5 6 8 9 10 11 20 14 24 52 56 B2 D9 D8 D3 E2 E3 F2 F3 G1 G2 G3 J9 H10 H9 H8 G9 G8 F10 F9 E8 F8 C10 B1 C3 J8 G3 H1 F8 E10 E9 E8 D10 D9 C10 D8 C3 C4 B2 D4 C2 D3 C1 D2 G2 E3 H2 K9 J10 I I I2Z I1U I O I2U O1 DMA Acknowledge - input from host DMA Request to host CS1FX# is the chip select for the task file registers CS3FX# is used to select the alternate status register and the Device Control register. This internally pulled-up signal is used to configure this device as a Master or a Slave. When this pin is grounded, this device is configured as a Master. When the pin is open, this device is configured as a Slave. The pin setting should remain the same from Power-on to Power-down. This is an I/O Read strobe generated by the host. This signal gates I/O data onto the bus from the chip. The I/O Write strobe pulse is used to clock I/O data into the chip. This output signal is asserted low when the device is indicating a word data transfer cycle. This signal is the active high Interrupt Request to the host. The Pass Diagnostic signal in the Master/Slave handshake protocol. The Drive Active/Slave Present signal in the Master/Slave handshake protocol. This input pin is the active low hardware reset from the host. I/O I1Z/O2 D[15:0] Data bus I I1Z A[2:0] are used to select one of eight registers in the Task File. IORD# IOWR# IOCS16# INTRQ PDIAG# DASP# RESET# 19 57 55 21 54 75 1 E9 D1 C2 D10 C1 H2 K10 F1 H9 H8 G1 J9 B10 A2 I I2Z O O I/O I/O I O2 O1 I1U/O1 I1U/O6 I2U (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 10 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet TABLE 3-1: Pin Assignments (Continued) (2 of 4) Pin No. Symbol WP_PD# 100-TQFP 85VFBGA 84TFBGA Pin Type I I/O Type1 I1U Name and Functions The WP_PD# pin can be used for either the Write Protect mode or Power-down mode, but only one mode is active at any time. The Write Protect or Power-down modes can be selected through the host command. The Write Protect mode is the factory default setting. Active Low Flash Media Chip Write Protect Connect this pin to the NAND flash media Write Protect pin Flash Media Chip Ready/Busy# Signal high is flash media ready signal. Low is busy. Active Low Flash Media Chip Read Active Low Flash Media Chip Write Active High Flash Media Chip Command Latch Enable Active High Flash Media Chip Address Latch Enable 62 D2 F9 Flash Media Interface FWP# FRDYbsy# FRE# FWE# FCLE FALE FAD15 FAD14 FAD13 FAD12 FAD11 FAD10 FAD9 FAD8 FAD7 FAD6 FAD5 FAD4 FAD3 FAD2 FAD1 FAD0 FCE6# FCE5# FCE4# FCE3# FCE2# FCE1# FCE0# FCE7#/ INTCLKEN 97 82 84 96 92 94 46 44 42 40 35 33 31 29 45 43 41 39 34 32 30 28 91 95 93 89 88 80 86 26 H7 J3 H3 J7 K6 H6 A3 B4 C5 A5 C7 A7 B8 B9 C4 A4 B5 C6 B7 C8 A8 A9 H5 K7 J6 J5 H4 K3 J4 C9 B4 A8 B7 A4 C6 B5 K8 K7 H6 J5 H5 K3 J3 J2 J7 J6 K6 K5 J4 H4 K2 H3 B6 C5 A5 A6 C7 B8 A7 J1 O I3D/O4 Active Low Flash Media Chip Enable pin This pin is sensed during the Power-on Reset (POR) to select an internal clock mode. If this pin is pulled up during the Power-on Reset then the internal clock is selected. O O4 Active Low Flash Media Chip Enable pin I/O I3U/O5 Flash Media Chip Low Byte Address/Data Bus pins I/O I3U/O5 Flash Media Chip High Byte Address/Data Bus pins O O5 O I O5 I4U (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 11 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet TABLE 3-1: Pin Assignments (Continued) (3 of 4) Pin No. Symbol SCIDOUT SCIDIN SCICLK FCE7#/ INTCLKEN 100-TQFP 85VFBGA 84TFBGA Pin Type O I I I/O I/O Type1 O4 I3U I3U I3D/O4 Name and Functions SCI interface data output SCI interface data input SCI interface clock Active Low Flash Media Chip Enable pin This pin is sensed during the Power-on Reset (POR) to select an Internal Clock mode. If this pin is pulled up during the Power-on Reset then the Internal Clock is selected. External Clock source input pin External Clock source output pin Serial Communication Interface (SCI) 79 78 77 26 J2 K2 K1 C9 A9 C8 C9 J1 External Clock Option EXTCLKIN EXTCLKOUT Miscellaneous VSS (IO) 100 99 2 12 27 36 64 74 90 98 25 51 38 87 76 7 69 50 13 J8 K9 A2 A6 A10 D4 E1 E10 H1 J10 K5 K8 A1 B10 B6 K4 J1 F1 G10 B3 B3 A3 I O I4Z O4 D7, G4 PWR Ground for I/O VSS (Core) VDD (IO) VDD (Core) VDDQ (IO) POR# TIE_DN G7 K4 B9 B1 H7 D1 PWR PWR PWR PWR I Analog Input2 Ground for Core VDD (3.3V) VDD (3.3V) VDDQ (5V/3.3V) for Host interface Power-on Reset (POR). Active Low Pins need to be connected to VSS. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 12 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet TABLE 3-1: Pin Assignments (Continued) (4 of 4) Pin No. Symbol DNU3 100-TQFP 85VFBGA 84TFBGA Pin Type I/O Type1 Name and Functions 15 16 17 18 37 47 48 49 58 59 60 61 63 81 83 85 E1 E2 F2 F3 F10 G8 G9 G10 H10 Do Not Use, must be left unconnected. T3-1.3 1241 1. Please refer to Section 12.1 for details. 2. Analog input for supply voltage detection 3. All DNU pins should not be connected. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 13 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 4.0 CAPACITY SPECIFICATION Table 4-1 shows the default capacity and specific settings for heads, sectors, and cylinders. Users can change the default settings in the drive ID table (see Table 11-4) for customization. If the total number of bytes is less than the default, the remaining space could be used as spares to increase the flash drive endurance. It should also be noted that if the total flash drive capacity exceeds the total default number of bytes, the flash drive endurance will be reduced. TABLE 16 MB 32 MB 48 MB 64 MB 96 MB 128 MB 192 MB 256 MB 384 MB 512 MB 640 MB 704 MB 768 MB 896 MB 1024 MB 1152 MB 1280 MB 1408 MB 1536 MB 1664 MB 1792 MB 1920 MB 2048 MB 2176 MB 2304 MB 2432 MB 2560 MB 2688 MB 2816 MB 2944 MB 3072 MB 3200 MB 3328 MB 3456 MB 3584 MB 3712 MB 3840 MB SST55LD019A/B 4-1: Default ATA Flash Drive Settings (1 of 2) Controller Version Total Bytes 16,023,552 32,047,104 48,037,888 64,028,672 96,075,776 128,057,344 192,413,696 256,901,120 384,491,520 512,483,328 640,475,136 704,471,040 768,466,944 896,974,848 1,024,966,656 1,152,442,368 1,280,434,176 1,408,425,984 1,536,417,792 1,664,409,600 1,792,401,408 1,920,393,216 2,048,385,024 2,176,376,832 2,304,368,640 2,432,360,448 2,560,352,256 2,688,344,064 2,816,335,872 2,944,327,680 3,072,319,488 3,200,311,296 3,328,303,104 3,456,294,912 3,584,286,720 3,712,278,528 3,840,270,336 Cylinders2 489 489 733 977 733 977 734 980 745 993 1241 1365 1489 1738 1986 2233 2481 2729 2977 3225 3473 3721 3969 4217 4465 4713 4961 5209 5457 5705 5953 6201 6449 6697 6945 7193 7441 Heads2 2 4 4 4 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Sectors2 32 32 32 32 32 32 32 32 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 Max LBA 31,296 62,592 93,824 125,056 187,648 250,112 375,808 501,760 750,960 1,000,944 1,250,928 1,375,920 1,500,912 1,751,904 2,001,888 2,250,864 2,500,848 2,750,832 3,000,816 3,250,800 3,500,784 3,750,768 4,000,752 4,250,736 4,500,720 4,750,704 5,000,688 5,250,672 5,500,656 5,750,640 6,000,624 6,250,608 6,500,592 6,750,576 7,000,560 7,250,544 7,500,528 Capacity1 (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 14 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet TABLE 4-1: Default ATA Flash Drive Settings (Continued) (2 of 2) Controller Version SST55LD019A/B SST55LD019B/C Total Bytes 3,968,262,144 4,096,253,952 6,001,164,288 8,001,552,384 10,001,940,480 12,001,296,384 14,001,684,480 16,001,040,384 18,001,428,480 SST55LD019C 20,001,816,576 22,001,172,480 24,001,560,576 26,001,948,672 28,001,304,576 30,001,692,672 32,001,048,576 Cylinders2 7689 7937 11628 15504 163833 163833 163833 163833 163833 163833 163833 163833 163833 163833 163833 163833 Heads2 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Sectors2 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 Max LBA 7,750,512 8,000,496 11,721,024 15,628,032 19,535,040 23,440,032 27,347,040 31,252,032 35,159,040 39,066,048 42,971,040 46,878,048 50,785,056 54,690,048 58,597,056 62,502,048 T4-1.5 1241 Capacity1 3968 MB 4096 MB 6 GB 8 GB 10 GB 12 GB 14 GB 16 GB 18 GB 20 GB 22 GB 24 GB 26 GB 28 GB 30 GB 32 GB 1. These flash drive capacities can only be manufactured by using the specified version of the ATA Flash Disk Controller. 2. Cylinders, Heads, and Sectors can be re-configured from the default settings during the manufacturing process. 3. Cylinders, Heads, and Sectors are not applicable for these capacities. Only LBA addressing applies. 4.1 Functional Specifications The SST55LD019A controller should be used when the random access performance needs to be maximized. The SST55LD019B controller is to be used when the sequential access performance needs to be maximized. The SST55LD019C controller is to be used when the flash drive capacity and sequential access performance need to be maximized. Table 4-2 shows the performance and the maximum capacity supported by each controller. TABLE Functions ATA Controller Supported Capacity ATA Controller Performance-Sustained Write speed ATA Controller Performance-Sustained Read speed 4-2: Functional Specification of SST55LD019A/B/C SST55LD019A up to 4 GB Up to 6.0 MB/sec Up to 10.0 MB/sec SST55LD019B up to 8 GB Up to 10.0 MB/sec Up to 10.0 MB/sec SST55LD019C 4 GB to 32 GB with external decoding1 logic Up to 10.0 MB/sec Up to 10.0 MB/sec T4-2.3 1241 1. Please refer to the reference schematics for high-capacity flash drive design. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 15 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 5.0 MANUFACTURING SUPPORT The ATA Flash Disk controller firmware contains a list of supported standard NAND flash media devices. Upon initial Poweron, the controller scans all connected flash media devices and reads their device ID. If the device ID matches the listed flash media devices in the ATA Flash Disk controller, the controller performs drive recognition based on the algorithm provided by the flash media suppliers, including setting up the bad block table, executing all the necessary handshaking routines for flash media support, and, finally, performing the low-level format. For Power-up timing specifications, please refer to Table 12-4. Please contact SST for the most current list of supported NAND Flash media devices. In the event that the NAND flash media device ID is not recognized by the ATA Flash Disk controller, the user has an option of adding this device to the controller device table through the manufacturing interface provided by SST. Please contact SST for the ATA Flash Disk controller manufacturing interface software. If the drive initialization fails, and a visual inspection is unable to determine the problem, the SST55LD019A / SST55LD019B / SST55LD019C ATA Flash Disk controller provides a comprehensive interface for manufacturing flow debug. This interface not only allows debug of the failure and manual reset of the initialization process, but also allows customization of user definable options. 5.1 ATA/IDE Interface The ATA Flash Disk controller interface can be used for manufacturing support. SST provides an example of a DOS-based solution (an executable routine downloadable from SST's web site) for manufacturing debug and rework. 5.2 Serial Communication Interface (SCI) For additional manufacturing flexibility, the SCI bus can be used for manufacturing error reporting. The SCI consists of 3 active signals: SCIDOUT, SCIDIN, and SCICLK. 6.0 EXTERNAL CLOCK INTERFACE The external clock interface allows ATA Flash Disk controller operation from an external clock source generated by an RC circuit. Do not use a free running clock as input to the EXTCLKIN pin; an RC circuit must be used. Contact SST for reference circuit and recommended external clock settings. While the controller has an internal clock source, the external clock source allows slowing of the system clock operation to limit the peak current and overcome additional bus loading. The external clock interface consists of three signals: INTCLKEN, EXTCLKIN, and EXTCLKOUT. The INTCLKEN pin selects between external and internal clock sources for the ATA Flash Disk controller. If this pin is pulled high before device Power-on, then the internal clock source is selected; otherwise, the external clock source is selected. The EXTCLKIN and EXTCLKOUT signals are the input and output clock signals, respectively. 7.0 SECURITY FEATURES The SST55LD019A/B/C ATA Flash Disk Controller offers added data protection for applications where data security is of the utmost importance. The secure features are: 1. Protection zones - Customer can enable up to 4 independent protection zones, with two options: Read-only or Hidden (Read and Write protected) within each protected zone. If protection zones are not enabled the data is unprotected (default configuration). 2. Password protection - Accessing information within the protected zones can be only achieved through a customer-unique password. 3. Purge command - The system can issue a Purge command to erase all information stored in the flash media. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 16 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 8.0 CONFIGURABLE WRITE PROTECT/POWER-DOWN MODES The WP_PD# pin can be used for either Write Protect mode or Power-down mode, but only one mode is active at any time. Either mode can be selected through the host command, Set-WP_PD#-Mode, explained in Section 11.2.1.31. Once the mode is set with this command, the device will stay in the configured mode until the next time this command is issued. Power-off or reset will not change the configured mode. 8.1 Write Protect Mode When the device is configured in the Write Protect mode, the WP_PD# pin offers extended data protection. This feature can be either selected through a jumper or host logic to protect the stored data from inadvertent system writes or erases, and viruses. The Write Protect feature protects the full address space of the data stored on the flash media. In the Write Protect mode, the WP_PD# pin should be asserted prior to issuing the destructive commands: Erase-Sector, Format-Track, Write-DMA, Write-Long-Sector, Write-Multiple, Write-Multiple-without-Erase, Write-Sector(s), Write-Sectorwithout-Erase, or Write-Verify. This will force the ATA Flash Disk Controller to reject any destructive commands from the ATA interface. All destructive commands will return 51H in the Status register and 04H in the Error register signifying an invalid command. All non-destructive commands will be executed normally. 8.2 Power-down Mode When the device is configured in the Power-down mode, if the WP_PD# pin is asserted during a command, the ATA disk controller completes the current command and returns to the standby mode immediately to save power. Afterwards, the device will not accept any other commands. Only a Power-on Reset (POR) or hardware reset will bring the device to normal operation with the WP_PD# pin de-asserted. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 17 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 9.0 POWER-ON AND BROWN-OUT RESET CHARACTERISTICS Please contact SST to obtain ATA Flash Disk controller reference design schematics including the POR# circuit for commercial and industrial ATA Flash Disk controller offerings. TR 10% TF 10% 90% VDD/POR# 90% 1298 F01.1 FIGURE TABLE Item 9-1: Power-on and Brown-out Reset Timing (Commercial Temperature) 9-1: Power-on and Brown-out Reset Timing (Commercial Temperature) Symbol Time1 TR TF Min Max 200 200 Units ms ms T9-1.0 1241 VDD/POR# Rise VDD/POR# Fall Time2 1. VDD Rise Time should be faster than or equal to POR# Rise Time. 2. VDD Fall Time should be slower than or equal to POR# Fall Time. VDD 90% 90% POR# TW TD 1298 F01b.0 FIGURE TABLE Item 9-2: Power-on and Brown-out Reset Timing (Industrial Temperature) 9-2: Power-on and Brown-out Reset Timing (Industrial Temperature) Symbol TW TD Min 0.1 30 Max Units ms s T9-2.0 1241 POR Wait Time Brown-out Delay Time (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 18 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 10.0 I/O TRANSFER FUNCTION The default operation for the ATA Flash Disk Controller is 16-bit. However, if the host issues a Set-Feature command to enable 8-bit mode, the ATA Flash Disk Controller permits 8-bit data access. The following table defines the function of various operations. TABLE 10-1: I/O Function Function Code Invalid Mode Standby Mode Task File Write Task File Read Data Register Write Data Register Read Control Register Write Alt Status Read Drive Address CS3FX# VIL VIH VIH VIH VIH VIH VIL VIL VIL CS1FX# VIL VIH VIL VIL VIL VIL VIH VIH VIH A0-A2 X X 1-7H 1-7H 0 0 6H 6H 7H IORD# X X VIH VIL VIH VIL VIH VIL VIL IOWR# X X VIL VIH VIL VIH VIL VIH VIH D15-D8 Undefined High Z X High Z In1 Out1 X High Z High Z D7-D0 Undefined High Z Data In Data Out In Out Control In Status Out Data Out T10-1.0 1241 1. If 8-bit data transfer mode is enabled. In 8-bit data transfer mode, High Byte is undefined for Data Out. For Data In, X can be VIH or VIL, but no other value. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 19 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.0 SOFTWARE INTERFACE 11.1 ATA Flash Disk Controller Drive Register Set Definitions and Protocol This section defines the drive registers for the ATA Flash Disk Controller and the protocol used to address them. 11.1.1 ATA Flash Disk Controller Addressing The I/O decoding for an ATA Flash Disk Controller is shown in Table 11-1. TABLE 11-1: Task File Registers Registers CS3FX# 1 1 1 1 1 1 1 1 0 0 CS1FX# 0 0 0 0 0 0 0 0 1 1 A2 0 0 0 0 1 1 1 1 1 1 A1 0 0 1 1 0 0 1 1 1 1 A0 0 1 0 1 0 1 0 1 0 1 IORD# = 0 (IOWR#=1) Data (Read) Error Sector Count Sector Number (LBA 7-0) Cylinder Low (LBA 15-8) Cylinder High (LBA 23-16) Drive/Head Status Alternate Status Drive Address IOWR# = 0 (IORD#=1) Data (Write) Feature Sector Count Sector Number (LBA 7-0) Cylinder Low (LBA 15-8) Cylinder High (LBA 23-16) Drive/Head Command Device Control Reserved T11-1.0 1241 11.1.2 ATA Flash Disk Controller Registers The following section describes the hardware registers used by the host software to issue commands to the ATA Flash Disk Controller. These registers are often collectively referred to as the Task File registers. The registers are only selectable through CS3FX#, CS1FX#, and A2-A0 signals. 11.1.2.1 Data Register (Read/Write) This 16-bit register is used to transfer data blocks between the device data buffer and the host. It is also the register through which sector information is transferred on a Format-Track command. Data transfer can be performed in PIO mode. 11.1.2.2 Error Register (Read Only) This register contains additional information about the source of an error when an error is indicated in bit 0 of the Status register. The bits are defined as follows: D7 BBK D6 UNC D5 0 D4 IDNF D3 0 D2 ABRT D1 0 D0 AMNF Reset Value 0000 0000b Symbol BBK UNC IDNF ABRT Function This bit is set when a Bad Block is detected. This bit is set when an Uncorrectable Error is encountered. The requested sector ID is in error or cannot be found. This bit is set if the command has been aborted because of an ATA Flash Disk Controller status condition: (Not Ready, Write Fault, etc.) or when an invalid command has been issued. It is required that the host retry any media access command (such as ReadSectors and Write-Sectors) that ends with an error condition. This bit is set in case of a general error. S71241-04-000 12/06 AMNF (c)2006 Silicon Storage Technology, Inc. 20 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.1.2.3 Feature Register (Write Only) This register provides information regarding features of the ATA Flash Disk Controller that the host can utilize. 11.1.2.4 Sector Count Register This register contains the numbers of sectors of data requested to be transferred on a Read or Write operation between the host and the ATA Flash Disk Controller. If the value in this register is zero, a count of 256 sectors is specified. If the command was successful, this register is zero at command completion. If not successfully completed, the register contains the number of sectors that need to be transferred in order to complete the request. 11.1.2.5 Sector Number (LBA 7-0) Register This register contains the starting sector number or bits 7-0 of the Logical Block Address (LBA) for any ATA Flash Disk Controller data access for the subsequent command. 11.1.2.6 Cylinder Low (LBA 15-8) Register This register contains the low order 8 bits of the starting cylinder address or bits 15-8 of the Logical Block Address. 11.1.2.7 Cylinder High (LBA 23-16) Register This register contains the high order bits of the starting cylinder address or bits 23-16 of the Logical Block Address. 11.1.2.8 Drive/Head (LBA 27-24) Register The Drive/Head register is used to select the drive and head. It is also used to select LBA addressing instead of cylinder/ head/sector addressing. The bits are defined as follows: D7 1 D6 LBA D5 1 D4 D3 D2 D1 D0 Reset Value 1010 0000b DRV HS3 HS2 HS1 HS0 Symbol LBA Function LBA is a flag to select either Cylinder/Head/Sector (CHS) or Logical Block Address mode (LBA). When LBA=0, Cylinder/Head/Sector mode is selected. When LBA=1, Logical Block Address is selected. In Logical Block mode, the Logical Block Address is interpreted as follows: LBA7-LBA0: Sector Number register D7-D0. LBA15-LBA8: Cylinder Low register D7-D0. LBA23-LBA16: Cylinder High register D7-D0. LBA27-LBA24: Drive/Head register bits HS3-HS0. DRV HS3 HS2 HS1 HS0 DRV is the drive number. When DRV=0 (Master), Master is selected. When DRV=1 (Slave), Slave is selected. When operating in the Cylinder, Head, Sector mode, this is bit 3 of the head number. It is Bit 27 in the Logical Block Address mode. When operating in the Cylinder, Head, Sector mode, this is bit 2 of the head number. It is Bit 26 in the Logical Block Address mode. When operating in the Cylinder, Head, Sector mode, this is bit 1 of the head number. It is Bit 25 in the Logical Block Address mode. When operating in the Cylinder, Head, Sector mode, this is bit 0 of the head number. It is Bit 24 in the Logical Block Address mode. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 21 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.1.2.9 Status & Alternate Status Registers (Read Only) These registers return the ATA Flash Disk Controller status when read by the host. Reading the Status register does clear a pending interrupt while reading the alternate Status register does not. The meaning of the status bits are described as follows: D7 BUSY D6 RDY D5 DWF D4 D3 D2 D1 D0 Reset Value 1000 0000b DSC DRQ CORR 0 ERR Symbol BUSY Function The busy bit is set when the ATA Flash Disk Controller has access to the command buffer and registers and the host is locked out from accessing the Command register and buffer. No other bits in this register are valid when this bit is set to a 1. RDY indicates whether the device is capable of performing ATA Flash Disk Controller operations. This bit is cleared at power up and remains cleared until the ATA Flash Disk Controller is ready to accept a command. This bit, if set, indicates a write fault has occurred. This bit is set when the ATA Flash Disk Controller is ready. The Data-Request bit is set when the ATA Flash Disk Controller requires that information be transferred either to or from the host through the Data register. This bit is set when a correctable data error has been encountered and the data has been corrected. This condition does not terminate a multi-sector Read operation. This bit is set when the previous command has ended in some type of error. The bits in the Error register contain additional information describing the error. It is required that the host retry any media access command (such as Read-Sectors and Write-Sectors) that end with an error condition. RDY DWF DSC DRQ CORR ERR 11.1.2.10 Device Control Register (Write Only) This register is used to control the ATA Flash Disk Controller interrupt request and to issue a software reset. This register can be written to even if the device is busy. The bits are defined as follows: D7 X D6 X D5 X D4 D3 D2 D1 D0 Reset Value 0000 1000b X 1 SW Rst -IEn 0 Symbol SW Rst -IEn Function This bit is set to 1 in order to force the ATA Flash Disk Controller to perform a software Reset operation. The chip remains in reset until this bit is reset to `0.' 0: The Interrupt Enable bit enables interrupts 1: Interrupts from the ATA Flash Disk Controller are disabled This bit is set to 0 at Power-on and Reset. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 22 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.1.2.11 Drive Address Register (Read Only) This register contains the inverted drive select and head select addresses of the currently selected drive. The bits in this register are as follows: D7 X D6 D5 D4 D3 D2 D1 D0 Reset Value x111 1110b -WTG Function -HS3 -HS2 -HS1 -HS0 -DS1 -DS0 Symbol -WTG -HS3 -HS2 -HS1 -HS0 -DS1 -DS0 This bit is 0 when a Write operation is in progress, otherwise, it is 1. This bit is the negation of bit 3 in the Drive/Head register. This bit is the negation of bit 2 in the Drive/Head register. This bit is the negation of bit 1 in the Drive/Head register. This bit is the negation of bit 0 in the Drive/Head register. This bit is 0 when drive 1 is active and selected. This bit is 0 when drive 0 is active and selected. 11.1.2.12 Command Register (Write Only) This register contains the command code being sent to the drive. Command execution begins immediately after this register is written. The executable commands, the command codes, and the necessary parameters for each command are listed in Table 11-2. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 23 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.2 ATA Flash Disk Controller Command Description This section defines the software requirements and the format of the commands the host sends to the ATA Flash Disk Controller. Commands are issued to the ATA Flash Disk Controller by loading the required registers in the command block with the supplied parameters, and then writing the command code to the Command register. The manner in which a command is accepted varies. There are three classes (see Table 11-2) of command acceptance, all dependent on the host not issuing commands unless the ATA Flash Disk Controller is not busy (BSY=0). 11.2.1 ATA Flash Disk Controller Command Set Table 11-2 summarizes the ATA Flash Disk Controller command set with the paragraphs that follow describing the individual commands and the task file for each. TABLE 11-2: ATA Flash Disk Controller Command Set (1 of 2) Command Check-Power-Mode Execute-Drive-Diagnostic Erase-Sector(s) Flush-Cache Format-Track Identify-Drive Idle Idle-Immediate Initialize-Drive-Parameters NOP Read-Buffer Read-DMA Read-Long-Sector Read-Multiple Read-Native-Max-Address Read-Sector(s) Read-Verify-Sector(s) Recalibrate Request-Sense Security-Disable-Password Security-Erase-Prepare Security-Erase-Unit Security-Freeze-Lock Security-Set-Password Security-Unlock Seek Set-Features Set-Max Set-Multiple-Mode Set-Sleep-Mode Set-WP_PD#-Mode Standby Standby-Immediate Code E5H or 98H 90H C0H E7H 50H ECH E3H or 97H E1H or 95H 91H 00H E4H C8H or C9H 22H or 23H C4H F8H 20H or 21H 40H or 41H 1XH 03H F6H F3H F4H F5H F1H F2H 7XH EFH F9H C6H E6H or 99H 8BH E2H or 96H E0H or 94H FR1 Y Y SC2 Y Y7 Y Y Y Y Y Y Y SN3 Y Y Y Y Y Y Y Y CY4 Y Y Y Y Y Y Y Y Y DH5 D8 D Y D Y8 D D D Y D D Y Y Y Y Y Y D D D D D D D D Y D Y D D D D D LBA6 Y Y Y Y Y Y Y Y Y Y - (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 24 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet TABLE 11-2: ATA Flash Disk Controller Command Set (Continued) (2 of 2) Command Translate-Sector Write-Buffer Write-DMA Write-Long-Sector Write-Multiple Write-Multiple-Without-Erase Write-Sector(s) Write-Sector(s)-Without-Erase Write-Verify 1. 2. 3. 4. 5. 6. 7. 8. Code 87H E8H CAH or CBH 32H or 33H C5H CDH 30H or 31H 38H 3CH FR1 - SC2 Y Y Y Y Y Y Y SN3 Y Y Y Y Y Y Y Y CY4 Y Y Y Y Y Y Y Y DH5 Y D Y Y Y Y Y Y Y LBA6 Y Y Y Y Y Y Y Y T11-2.1 1241 FR - Features register SC - Sector Count register SN - Sector Number register CY - Cylinder registers DH - Drive/Head register LBA - Logical Block Address mode supported (see command descriptions for use) Y - The register contains a valid parameter for this command. For the Drive/Head register: Y means both the ATA Flash Disk Controller and Head parameters are used; D means only the ATA Flash Disk Controller parameter is valid and not the Head parameter. 11.2.1.1 Check-Power-Mode - 98H or E5H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 7 6 5 4 Drive X X X X X 3 2 X 1 0 98H or E5H This command checks the power mode. Because the ATA Flash Disk Controller can recover from sleep in 200 ns, Idle mode is never enabled. ATA Flash Disk Controller sets BSY, sets the Sector Count register to 00H, clears BSY, and generates an interrupt. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 25 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.2.1.2 Erase-Sector(s) - C0H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 7 6 5 4 C0H Head (LBA 27-24) 3 2 1 0 The use of this command is not recommended. This command returns an error. 11.2.1.3 Execute-Drive-Diagnostic - 90H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X X X 7 6 5 4 90H X 3 2 1 0 This command performs the internal diagnostic tests implemented by the ATA Flash Disk Controller. If the Drive bit is ignored and the diagnostic command is executed by both the Master and the Slave with the Master responding with status for both devices. The diagnostic codes shown in Table 11-3 are returned in the Error register at the end of the command. TABLE11-3:Diagnostic Codes Code 01H 02H 03H 04H 05H 8XH Error Type No Error Detected Formatter Device Error Sector Buffer Error ECC Circuitry Error Controlling Microprocessor Error Slave Error T11-3.0 1241 (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 26 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.2.1.4 Flush-Cache - E7H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X X X 7 6 5 4 E7H X 3 2 1 0 This command causes the ATA Flash Disk Controller to complete writing data from its cache. The ATA Flash Disk Controller then clears BSY and generates an interrupt. 11.2.1.5 Format-Track - 50H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) X (LBA 7-0) Sector Count X 7 6 5 4 50H Head (LBA 27-24) 3 2 1 0 This command is accepted for host backward compatibility. The ATA Flash Disk Controller expects a sector buffer of data from the host to follow the command with the same protocol as the Write-Sector(s) command although the information in the buffer is not used by the ATA Flash Disk Controller. The use of this command is not recommended. 11.2.1.6 Identify-Drive - ECH Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X X X 7 6 5 4 ECH X 3 2 1 0 The Identify-Drive command enables the host to receive parameter information from the ATA Flash Disk Controller. This command has the same protocol as the Read-Sector(s) command. The parameter words in the buffer have the arrangement and meanings defined in Table 11-4. All reserved bits or words are zero. Table 11-4 gives the definition for each field in the Identify-Drive information. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 27 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet TABLE11-4:Identify-Drive Information Word Address 0 1 2 3 4 5 6 7-8 9 10-14 15-19 20 21 22 23-26 27-46 47 48 49 50 51 52 53 54 55 56 57-58 59 60-61 62 63 64 65 66 67 68 69-79 80 81 82 83 84 85-87 88 89 Default Value 044AH bbbbH1 0000H bbbbH1 0000H 0000H bbbbH1 bbbbH2 bbBFH eeeeH3 ddddH4 0002H 0200H 0004H aaaaH5 ccccH6 0001H 0000H 0B00H 0000H 0200H 0000H 0003H nnnnH nnnnH nnnnH nnnnH 0101H nnnnH 0000H 0n07H 0003H 0078H 0078H 0078H 0078H 0000H 007EH 0019H 706AH 410DH 4000H xxxxH 0000H xxxxH Total Bytes 2 2 2 2 2 2 2 4 2 10 10 2 2 2 8 40 2 2 2 2 2 2 2 2 2 2 4 2 4 2 2 2 2 2 2 2 22 2 2 2 2 2 6 2 2 Data Field Type Information General configuration bit Default number of cylinders Reserved Default number of heads Reserved Reserved Default number of sectors per track Number of sectors per device (Word 7 = MSW, Word 8 = LSW) Vendor Unique User-programmable serial number in ASCII SST preset, unique ID in ASCII Buffer type Buffer size in 512 Byte increments # of ECC bytes passed on Read/Write-Long-Sector Commands Firmware revision in ASCII. Big Endian Byte Order in Word User Definable Model number Maximum number of sectors on Read/Write-Multiple command Reserved Capabilities Reserved PIO data transfer cycle timing mode Reserved Translation parameters are valid Current numbers of cylinders Current numbers of heads Current sectors per track Current capacity in sectors (LBAs) (Word 57 = LSW, Word 58 = MSW) Multiple sector setting Total number of sectors addressable in LBA mode Reserved DMA data transfer is supported in ATA Flash Disk Controller Advanced PIO Transfer mode supported 120 ns cycle time support for Multi-word DMA Mode-2 120 ns cycle time support for Multi-word DMA Mode-2 PIO Mode-4 supported PIO Mode-4 supported Reserved ATA/ATAPI major version number ATA/ATAPI minor version number Features/command sets supported Features/command sets supported Features/command sets supported Features/command sets enabled Reserved Time required for security erase unit completion (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 28 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet TABLE11-4:Identify-Drive Information Word Address 90 91 92-127 128 129-159 160 161-255 1. 2. 3. 4. 5. 6. Default Value xxxxH xxxxH 0000H xxxxH 0000H xxxxH 0000H Total Bytes 2 2 72 2 62 2 190 Data Field Type Information Time required for enhanced security erase unit completion Current advanced power management value Reserved Security Status Vendor unique bytes CFA power mode description Reserved T11-4.3 1241 bbbb - default value set by controller. The selections could be user programmable. n - calculated data based on product configuration eeee - the default value is 2020H dddd - unique number of each device aaaa - any unique SST firmware revision cccc - default value is "xxxMB ATA Flash Disk" where xxx is the flash drive capacity. The user has an option to change the model number during manufacturing. 11.2.1.6.1 Word 0: General Configuration This field informs the host that this is a non-magnetic, hard sectored, removable storage device with a transfer rate greater than 10 MByte/sec and is not MFM encoded. 11.2.1.6.2 Word 1: Default Number of Cylinders This field contains the number of translated cylinders in the default translation mode. This value will be the same as the number of cylinders. 11.2.1.6.3 Word 3: Default Number of Heads This field contains the number of translated heads in the default translation mode. 11.2.1.6.4 Word 6: Default Number of Sectors per Track This field contains the number of sectors per track in the default translation mode. 11.2.1.6.5 Word 7-8: Number of Sectors This field contains the number of sectors per ATA Flash Disk Controller. This double word value is also the first invalid address in LBA translation mode. This field is only required by CF feature set support. 11.2.1.6.6 Word 10-19: Serial Number The contents of this field are right justified and padded with spaces (20H). The right-most ten bytes are a SST preset, unique ID. The left-most ten bytes are a user-programmable value with a default value of spaces. 11.2.1.6.7 Word 20: Buffer Type This field defines the buffer capability: 0002H: a dual ported multi-sector buffer capable of simultaneous data transfers to or from the host and the ATA Flash Disk Controller. 11.2.1.6.8 Word 21: Buffer Size This field defines the buffer capacity in 512 Byte increments. SST's ATA Flash Disk Controller has up to 2 sector data buffer for host interface. 11.2.1.6.9 Word 22: ECC Count This field defines the number of ECC bytes used on each sector in the Read- and Write-Long-Sector commands. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 29 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.2.1.6.10 Word 23-26: Firmware Revision This field contains the revision of the firmware for this product. 11.2.1.6.11 Word 27-46: Model Number This field is reserved for the model number for this product. 11.2.1.6.12 Word 47: Read-/Write-Multiple Sector Count This field contains the maximum number of sectors that can be read or written per interrupt using the Read-Multiple or Write-Multiple commands. 11.2.1.6.13 Word 49: Capabilities Bit Function 13 11 9 8 Standby Timer 0: forces sleep mode when host is inactive. IORDY Support 1: ATA Flash Disk Controller supports PIO Mode-4. LBA support 1: ATA Flash Disk Controller supports LBA mode addressing. DMA Support 1: DMA mode is supported. 11.2.1.6.14 Word 51: PIO Data Transfer Cycle Timing Mode This field defines the mode for PIO data transfer. ATA Flash Disk Controller supports up to PIO Mode-4. 11.2.1.6.15 Word 53: Translation Parameters Valid Bit Function 0 1 1: words 54-58 are valid and reflect the current number of cylinders, heads and sectors. 1: words 64-70 are valid to support PIO Mode-3 and 4. 11.2.1.6.16 Word 54-56: Current Number of Cylinders, Heads, Sectors/Track These fields contains the current number of user addressable Cylinders, Heads, and Sectors/Track in the current translation mode. 11.2.1.6.17 Word 57-58: Current Capacity This field contains the product of the current cylinders times heads times sectors. 11.2.1.6.18 Word 59: Multiple Sector Setting This field contains a validity flag in the Odd Byte and the current number of sectors that can be transferred per interrupt for Read/Write Multiple in the Even Byte. The Odd Byte is always 01H which indicates that the Even Byte is always valid. The Even Byte value depends on the value set by the Set Multiple command. The Even Byte of this word by default contains a 00H which indicates that Read/Write Multiple commands are not valid. 11.2.1.6.19 Word 60-61: Total Sectors Addressable in LBA Mode This field contains the number of sectors addressable for the ATA Flash Disk Controller in LBA mode only. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 30 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.2.1.6.20 Word 63: Multi-word DMA Transfer Mode This field identifies the multi-word DMA transfer modes supported by the ATA Flash Disk Controller and indicates the mode that is currently selected. Only one DMA mode can be selected at any given time. Bit 15-11 10 Function Reserved Multi-word DMA mode 2 selected 1: Multi-word DMA mode 2 is selected and bits 8 and 9 are cleared to 0 0: Multi-word DMA mode 2 is not selected. Multi-word DMA mode 1 selected 1: Multi-word DMA mode 1 is selected and 8 and 10 should be cleared to 0. 0: Multi-word DMA mode 1 is not selected. Multi-word DMA mode 0 selected 1: Multi-word DMA mode 0 is selected and bits 9 and 10 are cleared to 0. 0: Multi-word DMA mode 0 is not selected. Reserved Multi-word DMA mode 2 supported 1: Multi-word DMA mode 2 and below are supported and Bits 0 and 1 are set to 1. Multi-word DMA mode 1 supported 1: Multi-word DMA mode 1 and below are supported. Multi-word DMA mode 0 supported 1: Multi-word DMA mode 0 is supported. 9 8 7-3 2 1 0 11.2.1.6.21 Word 64: Advanced PIO Data Transfer Mode Bit Function 0 1 1: ATA Flash Disk Controller supports PIO Mode-3. 1: ATA Flash Disk Controller supports PIO Mode-4. 11.2.1.6.22 Word 65: Minimum Multi-word DMA Transfer Cycle Time Per Word This field defines the minimum Multi-word DMA transfer cycle time per word. This field defines, in nanoseconds, the minimum cycle time that the ATA Flash Disk Controller supports when performing Multi-word DMA transfers on a per word basis. SST's ATA Flash Disk Controller supports up to Multiword DMA Mode-2, so this field is set to 120ns. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 31 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.2.1.6.23 Word 66: Device Recommended Multi-word DMA Cycle Time This field defines the ATA Flash Disk Controller recommended Multi-word DMA transfer cycle time. This field defines, in nanoseconds, the minimum cycle time per word during a single sector host transfer while performing a multiple sector READ DMA or WRITE DMA command for any location on the media under nominal conditions. If a host runs at a faster cycle rate by operating at a cycle time of less than this value, the ATA Flash Disk Controller may negate DMARQ for flow control. The rate at which DMARQ is negated could result in reduced throughput despite the faster cycle rate. Transfer at this rate does not ensure that flow control will not be used, but implies that higher performance may result. SST's ATA Flash Disk Controller supports up to Multi-word DMA Mode-2, so this field is set to 120 ns. 11.2.1.6.24 Word 67: Minimum PIO Transfer Cycle Time Without Flow Control The ATA Flash Disk Controller's minimum cycle time is 120 ns. 11.2.1.6.25 Word 68: Minimum PIO Transfer Cycle Time With IORDY The ATA Flash Disk Controller's minimum cycle time is 120 ns, e.g., PIO Mode-4. 11.2.1.6.26 Word 80: Major Version Number If not 0000H or FFFFH, the device claims compliance with the major version(s) as indicated by bits (6:1) being set to one. Since ATA standards maintain downward compatibility, a device may set more than one bit. SST55LD019x supports ATA-1 to ATA-6. 11.2.1.6.27 Word 81: Minor Version Number If an implementer claims that the revision of the standard they used to guide their implementation does not need to be reported or if the implementation was based upon a standard prior to the ATA-3 standard, word 81 should be 0000H or FFFFH. A value of 0019H reported in word 81 indicates ATA/ATAPI-6 T13 1410D revision 3a guided the implementation. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 32 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.2.1.6.28 Words 82-84: Features/command sets supported Words 82, 83, and 84 indicate the features and command sets supported. Word 82 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word 83 The values in this word should not be depended on by host implementers. Bit 15 14 13-9 8 7-5 4 3 2 1 0 Word 84 The values in this word should not be depended on by host implementers. Bit 15 14 13-0 Function 0: Provides indication that the features/command sets supported words are valid 1: Provides indication that the features/command sets supported words are valid 0: Reserved Function 0: Provides indication that the features/command sets supported words are not valid 1: Provides indication that the features/command sets supported words are valid 0: Reserved 1: Set-Max security extension supported 0: Reserved 0: Removable Media Status feature set is not supported 1: Advanced Power Management feature set is supported 1: CFA feature set is supported 0: Read DMA Queued and Write DMA Queued commands are not supported 0: Download Microcode command is not supported Function 0: Obsolete 1: NOP command is supported 1: Read Buffer command is supported 1: Write Buffer command is supported 0: Obsolete 0: Host Protected Area feature set is not supported 0: Device Reset command is not supported 0: Service interrupt is not supported 0: Release interrupt is not supported 1: Look-ahead is supported 1: Write cache is supported 0: Packet Command feature set is not supported 1: Power Management feature set is supported 0: Removable Media feature set is not supported 1: Security Mode feature set is supported 0: SMART feature set is not supported (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 33 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.2.1.6.29 Words 85-87: Features/command sets enabled Words 85, 86, and 87 indicate features/command sets enabled. The host can enable/disable the features or command set only if they are supported in Words 82-84. Word 85 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word 86 Bit 15-9 8 7-5 4 3 2 1 0 Word 87 The values in this word should not be depended on by host implementers. Bit 15 14 13-0 (c)2006 Silicon Storage Technology, Inc. Function 0: Obsolete 0: NOP command is not enabled 1: NOP command is enabled 0: Read Buffer command is not enabled 1: Read Buffer command is enabled 0:Write Buffer command is not enabled 1: Write Buffer command is enabled 0: Obsolete 0: Host Protected Area feature set is not enabled 0: Device Reset command is not enabled 0: Service interrupt is not enabled 0: Release interrupt is not enabled 0: Look-ahead is not enabled 1: Look-ahead is enabled 0: Write cache is not enabled 1: Write cache is enabled 0: Packet Command feature set is not enabled 0: Power Management feature set is not enabled 1: Power Management feature set is enabled 0: Removable Media feature set is not enabled 0: Security Mode feature set has not been enabled via the Security Set Password command 1: Security Mode feature set has been enabled via the Security Set Password command 0: SMART feature set is not enabled Function 0: Reserved 1: Set-Max security extension supported 0: Reserved 0: Removable Media Status feature set is not enabled 0: Advanced Power Management feature set is not enabled via the Set Features command 1: Advanced Power Management feature set is enabled via the Set Features command 1: CFA feature set is enabled 0: Read DMA Queued and Write DMA Queued commands are not enabled 0: Download Microcode command is not enabled Function 0: Provides indication that the features/command sets supported words are valid 1: Provides indication that the features/command sets supported words are valid 0: Reserved S71241-04-000 12/06 34 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.2.1.6.30 Word 89: Time required for Security erase unit completion Word 89 specifies the time required for the Security Erase Unit command to complete. Value 0 1-254 255 Time Value not specified (Value * 2) minutes >508 minutes 11.2.1.6.31 Word 90: Time required for Enhanced security erase unit completion Word 90 specifies the time required for the Enhanced Security Erase Unit command to complete. Value 0 1-254 255 Time Value not specified (Value * 2) minutes >508 minutes 11.2.1.6.32 Word 91: Advanced power management level value Bit Function 7-0 Current Advanced Power Management level setting 11.2.1.6.33 Word 128: Security Status Bit Function 8 Security Level 1: Security mode is enabled and the security level is maximum 0: and security mode is enabled, indicates that the security level is high Enhanced security erase unit feature supported 1: Enhanced security erase unit feature set is supported 4 Expire 1: Security count has expired and Security Unlock and Security Erase Unit are command aborted until a Power-on reset or hard reset Freeze 1: Security is frozen Lock 1: Security is locked Enable/Disable 1: Security is enabled 0: Security is disabled Capability 1: ATA Flash Disk Controller supports security mode feature set 0: ATA Flash Disk Controller does not support security mode feature set 5 3 2 1 0 (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 35 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.2.1.6.34 Word 160: CFA Power Mode Description This word indicates the presence and status of a CFA feature set device that supports CFA power mode 1. Bit 13 Function Power Level 1 Command Support 1: Power Level 1 commands not supported 0: Power Level 1 commands supported Power Level 1 Command Enable 1: Power Level 1 Commands not enabled 0: Power Level 1 Commands enabled This field indicates the maximum average RMS current in mA required during 3.3V or 5V device operation in CFA power mode 1. 12 11-0 11.2.1.7 Idle - 97H or E3H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 7 6 5 4 Drive X X X Timer Count (5 msec increments) X 3 2 X 1 0 97H or E3H This command causes the ATA Flash Disk Controller to set BSY, enter the Idle mode, clear BSY and generate an interrupt. If the sector count is non-zero, it is interpreted as a timer count with each count being 5 milliseconds and the automatic Power-down mode is enabled. If the sector count is zero, the automatic Power-down mode is also enabled, the timer count is set to 3, with each count being 5 ms. Note that this time base (5 msec) is different from the ATA specification. 11.2.1.8 Idle-Immediate - 95H or E1H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 7 6 5 4 Drive X X X X X 3 2 X 1 0 95H or E1H This command causes the ATA Flash Disk Controller to set BSY, enter the Idle mode, clear BSY and generate an interrupt. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 36 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.2.1.9 Initialize-Drive-Parameters - 91H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 0 X Drive X X X Number of Sectors X 7 6 5 4 91H Max Head (no. of heads-1) 3 2 1 0 This command enables the host to set the number of sectors per track and the number of heads per cylinder. Only the Sector Count and the Drive/Head registers are used by this command. 11.2.1.10 NOP - 00H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X X X 7 6 5 4 00H X 3 2 1 0 This command always fails with the ATA Flash Disk Controller returning command aborted. 11.2.1.11 Read-Buffer - E4H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X X X 7 6 5 4 E4H X 3 2 1 0 The Read-Buffer command enables the host to read the current contents of the ATA Flash Disk Controller's sector buffer. This command has the same protocol as the Read-Sector(s) command (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 37 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.2.1.12 Read-DMA - C8H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 7 6 5 4 C8H Head (LBA 27-24) 3 2 1 0 This command executes in a similar manner to the Read-Sector(s) command except for the following: - the host initializes the DMA channel prior to issuing the command; - data transfers are qualified by DMARQ and are performed by the DMA channel; - the ATA Flash Disk Controller issues only one interrupt per command to indicate that data transfer has terminated and status is available. During the DMA transfer phase of a Read-DMA command, the ATA Flash Disk Controller will provide the status of the BSY bit or the DRQ bit until the command is completed. 11.2.1.13 Read-Multiple - C4H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 7 6 5 4 C4H Head (LBA 27-24) 3 2 1 0 Note: The current revision of the ATA Flash Disk Controller can support up to a block count of 1 as indicated in the Identify-Drive Command information. The Read-Multiple command is similar to the Read-Sector(s) command. Interrupts are not generated on every sector, but on the transfer of a block which contains the number of sectors defined by a Set Multiple command. Command execution is identical to the Read-Sectors operation except that the number of sectors defined by a Set Multiple command are transferred without intervening interrupts. DRQ qualification of the transfer is required only at the start of the data block, not on each sector. The block count of sectors to be transferred without intervening interrupts is programmed by the SetMultiple-Mode command, which must be executed prior to the Read-Multiple command. When the Read-Multiple command is issued, the Sector Count register contains the number of sectors (not the number of blocks or the block count) requested. If the number of requested sectors is not evenly divisible by the block count, as many full blocks as possible are transferred, followed by a final, partial block transfer. The partial block transfer is for n sectors, where n = remainder (sector count/block count). If the Read-Multiple command is attempted before the Set-Multiple-Mode command has been executed or when Read-Multiple commands are disabled, the Read-Multiple operation is rejected with an (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 38 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet Aborted Command error. Disk errors encountered during Read-Multiple commands are posted at the beginning of the block or partial block transfer, but DRQ is still set and the data transfer will take place as it normally would, including transfer of corrupted data, if any. Interrupts are generated when DRQ is set at the beginning of each block or partial block. The error reporting is the same as that on a Read-Sector(s) command. This command reads from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256 sectors. The transfer begins at the sector specified in the Sector Number register. At command completion, the Command Block registers contain the cylinder, head and sector number of the last sector read. If an error occurs, the read terminates at the sector where the error occurred. The Command Block registers contain the cylinder, head and sector number of the sector where the error occurred. The flawed data is pending in the sector buffer. Subsequent blocks or partial blocks are transferred only if the error was a correctable data error. All other errors cause the command to stop after transfer of the block which contained the error. 11.2.1.14 Read-Long-Sector - 22H or 23H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 7 6 5 4 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) X X 3 2 1 0 22H or 23H Head (LBA 27-24) The Read-Long-Sector command performs similarly to the Read-Sector(s) command except that it returns 516 Bytes of data instead of 512 Bytes. During a Read-Long-Sector command, the ATA Flash Disk Controller does not check the ECC bytes to determine if there has been a data error. Only singlesector Read-Long-Sector operations are supported. The transfer consists of 512 Bytes of data transferred in Word-Mode followed by 4 Bytes of ECC data transferred in Byte-Mode. This command has the same protocol as the Read-Sector(s) command. Use of this command is not recommended. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 39 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.2.1.15 Read-Native-Max-Address - F8H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X X X 7 6 5 4 F8H X 3 2 1 0 This command returns the native maximum address. The native maximum address is the highest address accepted by the device in the factory default condition. The native maximum address is the maximum address that is valid when using the Set-Max-Address command. The Read-Native-Max-Address command output will take the following format: Bit -> C/D/H Cyl High Cyl Low Sec Num Sec Cnt 7 6 X 5 4 Drive 3 2 1 0 Native max address (LBA 27:24) Native max address (LBA 23-16) Native max address (LBA 15-8) Native max address (LBA 7-0) X C/D/H Cyl High Cyl Low Sec Num Maximum native LBA bits (27:24) for native max address on the device. Drive indicates the selected device. Maximum native LBA bits (23:16) for native max address on the device. Maximum native LBA bits (15:8) for native max address on the device. Maximum native LBA bits (7:0) for native max address on the device. 11.2.1.16 Read-Sector(s) - 20H or 21H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 7 6 5 4 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 3 2 1 0 20H or 21H Head (LBA 27-24) This command reads from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256 sectors. The transfer begins at the sector specified in the Sector Number register. When this command is issued and after each sector of data (except the last one) has been read by the host, the ATA Flash Disk Controller sets BSY, puts the sector of data in the buffer, sets DRQ, clears BSY, and generates an interrupt. The host then reads the 512 Bytes of data from the buffer. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 40 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet At command completion, the Command Block registers contain the cylinder, head and sector number of the last sector read. If an error occurs, the read terminates at the sector where the error occurred. The Command Block registers contain the cylinder, head, and sector number of the sector where the error occurred. The flawed data is pending in the sector buffer. 11.2.1.17 Read-Verify-Sector(s) - 40H or 41H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 7 6 5 4 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 3 2 1 0 40H or 41H Head (LBA 27-24) This command is identical to the Read-Sectors command, except that DRQ is never set and no data is transferred to the host. When the command is accepted, the ATA Flash Disk Controller sets BSY. When the requested sectors have been verified, the ATA Flash Disk Controller clears BSY and generates an interrupt. Upon command completion, the Command Block registers contain the cylinder, head, and sector number of the last sector verified. If an error occurs, the verify terminates at the sector where the error occurs. The Command Block registers contain the cylinder, head and sector number of the sector where the error occurred. The Sector Count register contains the number of sectors not yet verified. 11.2.1.18 Recalibrate - 1XH Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X X X 7 6 5 4 1XH X 3 2 1 0 This command is effectively a no operation and is provided for compatibility purposes. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 41 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.2.1.19 Request-Sense - 03H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X X X 7 6 5 4 03H X 3 2 1 0 This command requests extended error information for the previous command. Table 11-5 defines the valid extended error codes for the ATA Flash Disk Controller. The extended error code is returned to the host in the Error register. TABLE11-5:Extended Error Codes Extended Error Code 00H 01H 09H 20H 21H 2FH 35H, 36H 11H 18H 05H, 30-34H, 37H, 3EH 10H, 14H 3AH 1FH 0CH, 38H, 3BH, 3CH, 3FH 03H 22H Description No Error Detected Self Test OK (No Error) Miscellaneous Error Invalid Command Invalid Address (Requested Head or Sector Invalid) Address Overflow (Address Too Large) Supply or generated Voltage Out of Tolerance Uncorrectable ECC Error Corrected ECC Error Self Test or Diagnostic Failed ID Not Found Spare Sectors Exhausted Data Transfer Error / Aborted Command Corrupted Media Format Write / Erase Failed Power Level 1 Disabled T11-5.0 1241 (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 42 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.2.1.20 Security-Disable-Password - F6H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X X X 7 6 5 4 F6H X 3 2 1 0 This command requests a transfer of a single sector of data from the host. Table 11-6 defines the content of this sector of information. If the password selected by Word 0 matches the password previously saved by the device, the device disables the lock mode. This command does not change the Master password that may be reactivated later by setting a User password. TABLE11-6:Security Password Data Content Word 0 Content Control Word Bit 0: Identifier 0: Compare User Password 1: Compare Master Password Bit 1-15: Reserved Password (32 Bytes) Reserved T11-6.0 1241 1-16 17-256 11.2.1.21 Security-Erase-Prepare - F3H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X X X 7 6 5 4 F3H X 3 2 1 0 This command is issued immediately before the Security-Erase-Unit command to enable device erasing and unlocking. This command prevents accidental erasure of the data in the flash media. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 43 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.2.1.22 Security-Erase-Unit - F4H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X X X 7 6 5 4 F4H X 3 2 1 0 This command requests transfer of a single sector of data from the host. Table 11-6 defines the content of this sector of information. If the password does not match the password previously saved by the ATA Flash Disk Controller, the ATA Flash Disk Controller rejects the command with command aborted. The Security-Erase-Prepare command should be completed immediately prior to the Security-Erase-Unit command. If the ATA Flash Disk Controller receives a Security-Erase-Unit command without an immediately prior Security-Erase-Prepare command, the ATA Flash Disk Controller aborts the SecurityErase-Unit command. 11.2.1.23 Security-Freeze-Lock - F5H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X X X 7 6 5 4 F5H X 3 2 1 0 The Security-Freeze-Lock command sets the ATA Flash Disk Controller to Frozen mode. After command completion, any other commands that update the ATA Flash Disk Controller Lock mode are rejected. Frozen mode is disabled by power off or hardware reset. If Security-Freeze-Lock is issued when the ATA Flash Disk Controller is in Frozen mode, the command executes and the ATA Flash Disk Controller remains in Frozen mode. After command completion, the sector count register should be set to 0. Commands disabled by Security-Freeze-Lock are: - Security-Set-Password - Security-Unlock - Security-Disable-Password - Security-Erase-Unit If security mode feature set is not supported, this command will be handled as an invalid command. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 44 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.2.1.24 Security-Set-Password - F1H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X X X 7 6 5 4 F1H X 3 2 1 0 This command requests a transfer of a single sector of data from the host. Table 11-7 defines the content of the sector of information. The data transferred controls the function of this command. TABLE11-7:Security Password Data Content Word 0 Content Control Word Bit 0: Identifier 0: Compare User Password 1: Compare Master Password Bit 1-15: Reserved Password (32 Bytes) Reserved T11-7.0 1241 1-16 17-256 Table 11-8 defines the interaction of the identifier and security level bits. TABLE11-8:Identifier and Security Level Bit Interaction Identifier Level User High Command result The password supplied with the command is saved as the new User password. The lock mode will be enabled from the next Power-on or hardware reset. The ATA Flash Disk Controller will then be unlocked by either the User password or the previously set Master password. User Maximum The password supplied with the command is saved as the new user password. The Lock mode will be enabled from the next Power-on reset or hardware reset. The ATA Flash Disk Controller will then be unlocked by only the User password. The Master password previously set is still stored in the ATA Flash Disk Controller will not be used to unlock the ATA Flash Disk Controller. High or This combination sets a Master password but does not enable or disable the Lock mode. Maximum The security level is not changed. T11-8.0 1241 Master (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 45 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.2.1.25 Security-Unlock- F2H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X X X 7 6 5 4 F2H X 3 2 1 0 This command requests transfer of a single sector of data from the host. Table 11-6 defines the content of this sector of information. If the identifier bit is set to Master and the device is in high security level, then the password supplied is compared with the stored Master password. If the device is in the maximum security level, then the unlock command will be rejected. If the identifier bit is set to user, then the device compares the supplied password with the stored User password. If the password compare fails, the device returns "command aborted" to the host and decrements the unlock counter. This counter is initially set to five and is decremented for each password mismatch when Security-Unlock is issued and the device is locked. Once this counter reaches zero, the Security-Unlock and SecurityErase-Unit commands are command aborted until after a Power-on reset or a hardware reset is received. Security-Unlock commands issued when the device is unlocked have no effect on the unlock counter. 11.2.1.26 Seek - 7XH Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) X (LBA 7-0) X X 7 6 5 4 7XH Head (LBA 27-24) 3 2 1 0 This command is effectively a no operation, although it does perform a range check of cylinder and head or LBA address and returns an error if the address is out of range. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 46 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.2.1.27 Set-Features - EFH Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X Config Feature 7 6 5 4 EFH X 3 2 1 0 This command is used by the host to establish or select certain features. Table 11-9 defines all features that are supported. TABLE11-9:Features Supported Feature 01H 02H 03H 05H 09H 0AH 55H 66H 69H 81H 82H 85H 89H 8AH 96H 97H 9AH BBH AAH CCH Operation Enable 8-bit data transfers. Enable Write cache Set transfer mode based on value in Sector Count register. Table 11-11 defines the values. Enable Advanced Power Management Enable Extended Power Operations Enable Power Level 1 commands Disable Read Look Ahead. Disable Power-on Reset (POR) establishment of defaults at software reset. NOP - Accepted for backward compatibility. Disable 8-bit data transfer. Disable Write Cache Disable Advanced Power Management Disable Extended Power operations Disable Power Level 1 commands NOP - Accepted for backward compatibility. Accepted for backward compatibility. Use of this Feature is not recommended. Set the host current source capability Allows trade-off between current drawn and Read/Write speed 4 Bytes of data apply on Read/Write-Long-Sector commands. Enable Read-Look-Ahead Enable Power-on Reset (POR) establishment of defaults at software reset. T11-9.0 1241 (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 47 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet Features 01H and 81H are used to enable and clear 8-bit data transfer mode. If the 01H feature command is issued all data transfers will occur on the low order D7-D0 data bus and the IOCS16# signal will not be asserted for data register accesses. Features 02H and 82H allow the host to enable or disable write cache in the ATA Flash Disk Controllers that implement write cache. When the subcommand Disable-Write-Cache is issued, the ATA Flash Disk Controller should initiate the sequence to flush cache to non-volatile memory before command completion. Feature 03H allows the host to select the transfer mode by specifying a value in the Sector Count register. The upper 5 bits define the type of transfer and the low order 3 bits encode the mode value. One PIO mode is selected at all times. The host may change the selected modes by the Set-Features command. Feature 05H allows the host to enable advanced power management. To enable advanced power management, the host writes the Sector Count register with the desired advanced power management level and then executes a Set-Features command with subcommand code 05H. The power management level is a scale from the lowest power consumption setting of 01H to the maximum performance level of FEH. Table 11-10 shows these values. TABLE11-10:Advanced Power Management Levels Level Maximum performance Intermediate power management levels without standby Minimum power consumption without standby Intermediate power management levels with standby Minimum power consumption with standby Reserved Reserved Sector Count Value FEH 81H-FDH 80H 02H-7FH 01H FFH 00H T11-10.0 1241 (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 48 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet Device performance may increase with increasing power management levels. Device power consumption may increase with increasing power management levels. The power management levels may contain discrete bands. For example, a ATA Flash Disk Controller may implement one power management method from 80H to A0H and a higher performance, higher power consumption method from level A1H to FEH. Feature 85H disables Advanced Power Management. Subcommand 85H may not be implemented on all devices that implement Set Features subcommand 05H. Features 0AH and 8AH are used to enable and disable Power Level 1 commands. Feature 0AH is the default feature for the ATA Flash Disk Controller with extended power. Features 55H and BBH are the default features for the ATA Flash Disk Controller; thus, the host does not have to issue this command with these features unless it is necessary for compatibility reasons. Feature code 9AH enables the host to configure the device to best meet the host system's power requirements. The host sets a value in the Sector Count register that is equal to one-fourth of the desired maximum average current (in mA) that the device should consume. For example, if the Sector Count register is set to 6, the device would be configured to provide the best possible performance without exceeding 24 mA. Upon completion of the command, the device responds to the host with the range of values supported by the device. The minimum value is set in the Cylinder Low register, and the maximum value is set in the Cylinder High register. The default value, after a power on reset, is to operate at the highest performance and therefore the highest current mode. The device will accept values outside this programmable range, but will operate either at the lowest power or highest performance as appropriate. Features 66H and CCH can be used to enable and disable whether the Power-on Reset (POR) Defaults will be set when a software reset occurs. TABLE11-11:Transfer Mode Values Mode PIO default mode PIO default mode, disable IORDY PIO flow control transfer mode Multi-word DMA mode Reserved Bits [7:3] 00000b 00000b 00001b 00100b Other Bits [2:0] 000b 001b mode1 mode1 N/A T11-11.0 1241 1. Mode = transfer mode number, all other values are not valid 11.2.1.28 Set-Max - F9H Individual Set-Max commands are identified by the value placed in the Features register. Table 11-12 shows these Features register values. TABLE11-12:Set-Max Features register values Value 00H 01H 02H 03H 04H 05H-FFH Command Obsolete Set-Max-Set-Password Set-Max-Lock Set-Max-Unlock Set-Max-Freeze-Lock Reserved T11-12.0 1241 (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 49 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.2.1.28.1 Set-Max-Address - F9H Bit -> Command (7) 1 C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) LBA 1 Drive 7 6 5 4 F9H Native max address head number or Set-Max LBA 3 2 1 0 Set-Max cylinder high or LBA Set-Max cylinder low or LBA Native max address sector number or Set-Max LBA X X VV The Set-Max-Address command must be immediately preceded by a successful execution of a ReadNative-Max-Address command. Otherwise the Set-Max-Address command will be interpreted as another Set-Max command or aborted as an invalid command. C/D/H LBA Drive Bits (3:0) Cyl High Cyl Low Sec Num Sec Cnt VV 1: The maximum address value is an LBA value. 0: The maximum address value is a CHS value. The selected device. The native max address head number (Identify-Device word 3 minus one) or LBA bits (27:24) value to be set. Contains the maximum cylinder high or LBA bits (23:16) value to be set Contains the maximum cylinder low or LBA bits (15:8) value to be set Contains the native max address sector number (Identify-Device word 6) or LBA bits (7:0) value to be set Value Volatile 1: The device preserves the maximum values over Power-on or hardware reset. 0: The device reverts to the most recent non-volatile maximum address value setting over Power-on or hardware reset. After successful command completion, all Read and Write access attempts to addresses greater than specified by the successful Set-Max-Address command is rejected with an IDNF error. Identify-Device response words 1, 54, 57, 58, 60, and 61 reflect the maximum address set with this command. Hosts should not issue more than one non-volatile Set-Max-Address command after a Power-on or hardware reset. Devices should report an IDNF error upon receiving a second non-volatile Set-Max-Address command after a Power-on or hardware reset. The contents of Identify-Device words and the max address will not be changed if a Set-Max-Address command fails. After a successful Set-Max-Address command using a new maximum cylinder number value the content of all Identify-Device words must comply with the following: 1. The content of words 3, 6, 55, and 56 are unchanged 2. The content of word 1 will equal (the new Set-Max cylinder number + 1) or 16,383, whichever is less 3. The content of words (61:60) equals [(the new content of word 1 as determined by the successful Set-MaxAddress command) * (the content of word 3) * (the content of word 6)] (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 50 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 4. If the content of words (61:60) as determined by a successful Set-Max-Address command is less than 16,514,064, then the content of word 54 should be equal to [(the content of words (61:60)) / ((the content of Identify-Device word 55) * (the content of word 56)] or 65,535, whichever is less. 5. If the content of word (61:60), as determined by a successful Set-Max-Address command, is greater than 16,514,064, then word 54 should equal the whole number result of [[(16,514,064) / [(the content of word 55) * (the content of word 56)]] or 65,535 whichever is less). The content of words (58:57) should be equal to [(the new content of word 54 as determined by the successful Set-Max-Address command) * (the content of word 55) * (the content of word 56)]. After a successful Set-Max-Address command using a new maximum LBA address the content of all IdentifyDevice words must comply with the following: * The content of words (61:60) should equal the new Maximum LBA address + 1. * If the content of words (61:60) is greater than 16,514,064 and if the device does not support CHS addressing, then the content of words 1, 3, 6, 54, 55, 56, and (58:57) should equal zero. If the device supports CHS addressing: * The content of words 3, 6, 55, and 56 are unchanged. * If the new content of words (61:60) is less than 16,514,064, then the content of word 1 should equal [(the new content of words (61:60)) / [(the content of word 3) * (the content of word 6)]] or 65,535, whichever is less. * If the new content of words (61:60) is greater than or equal to 16,514,064, then the content of word 1 should be equal to 16,383. * If the new content of words (61:60) is less than 16,514,064, then the content of word 54 should equal [(the new content of words (61:60)) / [(the content of word 55) * (the content of word 56)]]. * If the new content of words (61:60) is greater than or equal to 16,514,064, then the content of word 54 should equal 16,383. * Words (58:57) should equal [(the content of word 54) * (the content of word 55) * (the content of word 56). (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 51 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.2.1.28.2 Set-Max-Set-Password F9H with the content of the Features register equal to 01H. Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive N/A N/A N/A N/A 01H 7 6 5 4 F9H N/A 3 2 1 0 This command requests a transfer of a single sector of data from the host. Table 11-1 defines the content of this sector of information. The password is retained by the device until the next power cycle. When the device accepts this command, the device is in Set_Max_Locked state. If this command is immediately preceded by a Read-Native-Max-Address command, it will be interpreted as a Set-Max-Address command. TABLE11-13:Set-Max-Set-Password Data Content Word 0 1-16 17-255 Content Reserved Password (32 Bytes) Reserved T11-13.0 1241 11.2.1.28.3 Set-Max-Lock F9H with the content of the Features register equal to 02H. Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive N/A N/A N/A N/A 02H 7 6 5 4 F9H N/A 3 2 1 0 The Set-Max-Lock command sets the device into Set_Max_Locked state. After this command is completed, any other Set-Max commands except Set-Max-Unlock and Set-Max-Freeze-Lock are rejected. The device remains in this state until a power cycle or the acceptance of a Set-Max-Unlock or Set-Max-Freeze-Lock command. If this command is immediately preceded by a Read-Native-Max-Address command, it will be interpreted as a Set-Max-Address command. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 52 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.2.1.28.4 Set-Max-Unlock F9H with the content of the Features register equal to 03H. Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive N/A N/A N/A N/A 03H 7 6 5 4 F9H N/A 3 2 1 0 This command requests a transfer of a single sector of data from the host. Table 11-13 defines the content of this sector of information. The password supplied in the sector of data transferred will be compared with the stored Set-Max password. If the password compare fails, then the device returns command aborted and decrements the unlock counter. On the acceptance of the Set-Max-Lock command, this counter is set to a value of five and is decremented for each password mismatch when Set-Max-Unlock is issued and the device is locked. When this counter reaches zero, then the Set-Max-Unlock command returns "command aborted" until a power cycle. If the password compare matches, then the device transitions to the Set_Max_Unlocked state and all Set-Max commands will be accepted. If this command is immediately preceded by a Read-Native-Max-Address command, it will be interpreted as a Set-Max-Address command. 11.2.1.28.5 Set-Max-Freeze-Lock F9H with the content of the Features register equal to 04H. Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive N/A N/A N/A N/A 04H 7 6 5 4 F9H N/A 3 2 1 0 The Set-Max-Freeze-Lock command sets the device to Set_Max_Frozen state. After command completion any subsequent Set-Max commands are rejected. Commands disabled by Set-Max-Freeze-Lock are: - Set-Max-Address - Set-Max-Set-Password - Set-Max-Lock - Set-Max-Unlock If this command is immediately preceded by a Read-Native-Max-Address command, it will be interpreted as a Set-Max-Address command. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 53 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.2.1.29 Set-Multiple-Mode - C6H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X Sector Count X 7 6 5 4 C6H X 3 2 1 0 This command enables the ATA Flash Disk Controller to perform Read and Write-Multiple operations and establishes the block count for these commands. The Sector Count register is loaded with the number of sectors per block. Upon receipt of the command, the ATA Flash Disk Controller sets BSY to 1 and checks the Sector Count register. If the Sector Count register contains a valid value (see Section 11.2.1.6.12 for details) and the block count is supported, the value is loaded for all subsequent Read-Multiple and Write-Multiple commands and execution of those commands is enabled. If a block count is not supported, an Aborted Command error is posted, and Read-Multiple and Write-Multiple commands are disabled. If the Sector Count register contains 0 when the command is issued, Read and Write-Multiple commands are disabled. At power on, or after a hardware or (unless disabled by a Set Feature command) software reset, the default mode is Read and Write-Multiple disabled. 11.2.1.30 Set-Sleep-Mode - 99H or E6H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 7 6 5 4 Drive X X X X X 3 2 X 1 0 99H or E6H This command causes the ATA Flash Disk Controller to set BSY, enter the Sleep mode, clear BSY and generate an interrupt. Recovery from sleep mode is accomplished by simply issuing another command (a reset is permitted but not required). Sleep mode is also entered when internal timers expire so the host does not need to issue this command except when it wishes to enter Sleep mode immediately. The default value for the timer is 15 milliseconds. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 54 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.2.1.31 Set-WP_PD#-Mode - 8BH Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive 6EH 44H 72H 50H 55H or AAH 7 6 5 4 8BH X 3 2 1 0 This command configures the WP_PD# pin for either the Write Protect mode or the Power-down mode. When the host sends this command to the device with the value AAH in the feature register, the WP_PD# pin is configured for the Write Protect mode described in Section 8.1. The Write Protect mode is the factory default setting. When the host sends this command to the device with the value 55H in the feature register, WP_PD# is configured for the Power-down mode. All values in the C/D/H register, the Cylinder Low register, the Cylinder High register, the Sector Number register, the Sector Count register, and the Feature register need to match the values shown above, otherwise, the command will be treated as an invalid command. Once the mode is set with this command, the device will stay in the configured mode until the next time this command is issued. Power-off or reset will not change the configured mode. 11.2.1.32 Standby - 96H or E2H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 7 6 5 4 Drive X X X X X 3 2 X 1 0 96H or E2H This command causes the ATA Flash Disk Controller to set BSY, enter the Sleep mode (which corresponds to the ATA "Standby" mode), clear BSY and return the interrupt immediately. Recovery from sleep mode is accomplished by simply issuing another command (a reset is not required). (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 55 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.2.1.33 Standby-Immediate - 94H or E0H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 7 6 5 4 Drive X X X X X 3 2 X 1 0 94H or E0H This command causes the ATA Flash Disk Controller to set BSY, enter the Sleep mode (which corresponds to the ATA "Standby" mode), clear BSY and return the interrupt immediately. Recovery from sleep mode is accomplished by simply issuing another command (a reset is not required). 11.2.1.34 Translate-Sector - 87H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) X X 7 6 5 4 87H Head (LBA 27-24) 3 2 1 0 This command allows the host a method of determining the exact number of times a user sector has been erased and programmed. The controller responds with a 512 Byte buffer of information containing the desired cylinder, head, and sector, including its logical address, and the Hot Count, if available, for that sector. Table 11-14 represents the information in the buffer. Please note that this command is unique to the ATA Flash Disk Controller. TABLE11-14:Translate Sector Information Address 00H-01H 02H 03H 04H-06H 07H-12H 13H 14H-17H 18H-1AH 1BH-1FFH Information Cylinder MSB (00), Cylinder LSB (01) Head Sector LBA MSB (04) - LSB (06) Reserved Erased Flag (FFh) = Erased; 00h = Not Erased Reserved Hot Count MSB (18) - LSB (1A)1 Reserved T11-14.0 1241 1. A value of 0 indicates Hot Count is not supported. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 56 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.2.1.35 Write-Buffer - E8H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X X X 7 6 5 4 E8H X 3 2 1 0 The Write-Buffer command enables the host to overwrite contents of the ATA Flash Disk Controller's sector buffer with any data pattern desired. This command has the same protocol as the WriteSector(s) command and transfers 512 Bytes. 11.2.1.36 Write-DMA - CAH Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 7 6 5 4 CAH Head (LBA 27-24) 3 2 1 0 This command executes in a similar manner to Write-Sector(s) except for the following: - the host initializes the DMA channel prior to issuing the command; - data transfers are qualified by DMARQ and are performed by the DMA channel; - the ATA Flash Disk Controller issues only one interrupt per command to indicate that data transfer has terminated and status is available. During the execution of a WRITE DMA command, the ATA Flash Disk Controller will provide status of the BSY bit or the DRQ bit until the command is completed. 11.2.1.37 Write-Long-Sector - 32H or 33H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 7 6 5 4 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) X X 3 2 1 0 32H or 33H Head (LBA 27-24) This command is similar to the Write-Sector(s) command except that it writes 516 Bytes instead of 512 Bytes. Only single sector Write-Long-Sector operations are supported. The transfer consists of 512 Bytes of data transferred in Word-Mode followed by 4 Bytes of ECC transferred in Byte-Mode. Because of the unique nature of the solid-state ATA Flash Disk Controller, the 4 Bytes of ECC transferred by the (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 57 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet host may be used by the ATA Flash Disk Controller. The ATA Flash Disk Controller may discard these 4 Bytes and write the sector with valid ECC data. This command has the same protocol as the WriteSector(s) command. Use of this command is not recommended. 11.2.1.38 Write-Multiple - C5H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive Cylinder High Cylinder Low Sector Number Sector Count X 7 6 5 4 C5H Head 3 2 1 0 Note: The current revision of the ATA Flash Disk Controller can support up to a block count of 1 as indicated in the Identify-Drive Command information. This command is similar to the Write-Sectors command. The ATA Flash Disk Controller sets BSY within 400 ns of accepting the command. Interrupts are not presented on each sector but on the transfer of a block which contains the number of sectors defined by Set Multiple. Command execution is identical to the Write-Sectors operation except that the number of sectors defined by the Set Multiple command is transferred without intervening interrupts. DRQ qualification of the transfer is required only at the start of the data block, not on each sector. The block count of sectors to be transferred without intervening interrupts is programmed by the SetMultiple-Mode command, which must be executed prior to the Write-Multiple command. When the Write-Multiple command is issued, the Sector Count register contains the number of sectors (not the number of blocks or the block count) requested. If the number of requested sectors is not evenly divisible by the sector/block, as many full blocks as possible are transferred, followed by a final, partial block transfer. The partial block transfer is for n sectors, where: n = remainder (sector count/block). If the Write-Multiple command is attempted before the Set-Multiple-Mode command has been executed or when Write-Multiple commands are disabled, the Write-Multiple operation will be rejected with an aborted command error. Errors encountered during Write-Multiple commands are posted after the attempted writes of the block or partial block transferred. The Write command ends with the sector in error, even if it is in the middle of a block. Subsequent blocks are not transferred in the event of an error. Interrupts are generated when DRQ is set at the beginning of each block or partial block. The Command Block registers contain the cylinder, head and sector number of the sector where the error occurred and the Sector Count register contains the residual number of sectors that need to be transferred for successful completion of the command e.g. each block has 4 sectors, a request for 8 sectors is issued and an error occurs on the third sector. The Sector Count register contains 6 and the address is that of the third sector. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 58 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.2.1.39 Write-Multiple-Without-Erase - CDH Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive Cylinder High Cylinder Low Sector Number Sector Count X 7 6 5 4 CDH Head 3 2 1 0 Use of this command is not recommended, but it is supported as Write-Multiple command for backward compatibility. 11.2.1.40 Write-Sector(s) - 30H or 31H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 7 6 5 4 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 3 2 1 0 30H or 31H Head (LBA 27-24) This command writes from 1 to 256 sectors as specified in the Sector Count register. A sector count of zero requests 256 sectors. The transfer begins at the sector specified in the Sector Number register. When this command is accepted, the ATA Flash Disk Controller sets BSY, then sets DRQ and clears BSY, then waits for the host to fill the sector buffer with the data to be written. No interrupt is generated to start the first host transfer operation. No data should be transferred by the host until BSY has been cleared by the host. For multiple sectors, after the first sector of data is in the buffer, BSY will be set and DRQ will be cleared. After the next buffer is ready for data, BSY is cleared, DRQ is set and an interrupt is generated. When the final sector of data is transferred, BSY is set and DRQ is cleared. It will remain in this state until the command is completed at which time BSY is cleared and an interrupt is generated. If an error occurs during a write of more than one sector, writing terminates at the sector where the error occurs. The Command Block registers contain the cylinder, head and sector number of the sector where the error occurred. The host may then read the command block to determine what error has occurred, and on which sector. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 59 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.2.1.41 Write-Sector(s)-Without-Erase - 38H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 7 6 5 4 38H Head (LBA 27-24) 3 2 1 0 Use of this command is not recommended, but it is supported as Write-Sector(s) command for backward compatibility. 11.2.1.42 Write-Verify - 3CH Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 7 6 5 4 3CH Head (LBA 27-24) 3 2 1 0 This command is similar to the Write-Sector(s) command, except each sector is verified immediately after being written. This command has the same protocol as the Write-Sector(s) command. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 60 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 11.2.2 Error Posting The following table summarizes the valid status and error values for the ATA Flash Disk Controller command set. TABLE 11-15: Error and Status Register1 (1 of 2) Error Register Command Check-Power-Mode Execute-Drive-Diagnostic2 Erase-Sector(s) Flush-Cache Format-Track Identify-Drive Idle Idle-Immediate Initialize-Drive-Parameters NOP Read-Buffer Read-DMA Read-Long-Sector Read-Multiple Read-Native-Max-Address Read-Sector(s) Read-Verify-Sector(s) Recalibrate Request-Sense Security-Disable-Password Security-Erase-Prepare Security-Erase-Unit Security-Freeze-Lock Security-Set-Password Security-Unlock Seek Set-Features Set-Max Set-Multiple-Mode Set-Sleep-Mode Set-WP_PD#-Mode Standby Standby-Immediate Translate-Sector Write-Buffer Write-DMA Write-Long-Sector Write-Multiple Write-Multiple-Without-Erase V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V BBK UNC IDNF ABRT V AMNF RDY V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V Status Register DWF DSC V V V V V V V V V CORR ERR V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 61 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet TABLE 11-15: Error and Status Register1 (Continued) (2 of 2) Error Register Command Write-Sector(s) Write-Sector(s)-Without-Erase Write-Verify Invalid-Command-Code BBK V V V UNC IDNF V V V ABRT V V V V AMNF V V V RDY V V V V V V V V Status Register DWF DSC V V V V CORR ERR V V V V T11-15.3 1241 1. The host is required to reissue any media access command (such as Read-Sector and Write Sector) that ends with an error condition. 2. See Table 11-3 V = valid on this command. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 62 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 12.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D.C. Voltage on Pins1 I3, I4, O4, and O5 to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Pins1 I3, I4, O4, and O5 to Ground Potential . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V D.C. Voltage on Pins1 I1, I2, O1, O2, and O6 to Ground Potential. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDDQ+0.5V Transient Voltage (<20 ns) on Pins1 I1, I2, O1, O2, and O6 to Ground Potential. . . . . . . . . . . . . -2.0V to VDDQ+2.0V Package Power Dissipation Capability (TA = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Through Hole Lead Soldering Temperature (10 Seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C for 10 seconds Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Please refer to Table 3-1 for pin assignment information. 2. Outputs shorted for no more than one second. No more than one output shorted at a time. TABLE 12-1: Absolute Maximum Power Pin Stress Ratings Parameter Input Power Voltage on any flash media interface pin with respect to VSS Voltage on all other pins with respect to VSS Symbol VDDQ VDD Conditions -0.3V min to 6.5V max -0.3V min to 4.0V max -0.5V min to VDD + 0.5V max -0.5V min to VDDQ + 0.5V max T12-1.0 1241 TABLE 12-2: Operating Range Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VDD 3.135-3.465V 3.135-3.465V VDDQ 4.5-5.5V; 3.135-3.465V 4.75-5.25V; 3.135-3.465V TABLE 12-3: AC Conditions of Test Input Rise/Fall Time . . . . . . . . . . . . . . 10 ns Output Load . . . . . . . . . . . . . . . . . . . . CL = 100 pF See Figure 12-1 Note: All AC specifications are guaranteed by design. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 63 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet TABLE 12-4: Recommended System Power-on Timing Symbol TPU-INITIAL Parameter Drive Initialization to Ready Typical 3 sec + (0.5 sec/ GByte) 200 200 400 400 Maximum 100 500 500 1000 1000 Units sec ms ms ms ms T12-4.2 1241 TPU-READY11 SST55LD019A/B: Host Power-on/Reset to Ready Operation TPU-WRITE11 TPU-READY21 SST55LD019C: TPU-WRITE21 Host Power-on/Reset to Write Operation Host Power-on/Reset to Ready Operation Host Power-on/Reset to Write Operation 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 12-5: Capacitance (Ta = 25C, f=1 MHz, other pins open) Parameter CI/O1 CIN 1 Description I/O Pin Capacitance Input Capacitance Test Condition VI/O = 0V VIN = 0V Maximum 15 pF 9 pF T12-5.0 1241 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 12-6: Reliability Characteristics Symbol ILTH1 Parameter Latch Up Minimum Specification 100 + IDD Units mA Test Method JEDEC Standard 78 T12-6.0 1241 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 64 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 12.1 DC Characteristics TABLE 12-7: DC Characteristics for Media Interface Symbol VIH3 VIL3 IIL3 IU3 ID3 VT+4 VT-4 IIL4 IU4 VOH4 VOL4 IOH4 IOL4 VOH5 VOL5 IOH5 IOL5 O5 O4 Type I3 I3Z I3U I3D I4 I4Z I4U Parameter Input Voltage Input Leakage Current Input Pull-Up Current Input Pull-Down Current Input Voltage Schmitt Trigger 0.75 Input Leakage Current Input Pull-Up Current Output Voltage Output Current Output Current Output Voltage Output Current Output Current 2.4 0.4 -3 3 mA mA -10 -8 2.4 0.4 -1.5 1.5 mA mA V 10 -50 uA uA V Min 2.0 0.8 -10 -8 30 10 -50 200 2.5 uA uA uA V Max Units V Conditions VDD=VDD Max VDD=VDD Min VIN = GND to VDD, VDD = VDD Max VIN = GND, VDD = VDD Max VIN = VDD, VDD = VDD Max VDD = VDD Max VDD = VDD Min VIN = GND to VDD, VDD = VDD Max VIN = GND, VDD = VDD Max IOH4=IOH4 Min IOL4=IOL4 Max VDD=VDD Min VDD=VDD Min IOH5=IOH5 Min IOL5=IOL5 Max VDD=VDD Min VDD=VDD Min T12-7.0 1241 (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 65 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet TABLE 12-8: DC Characteristics for Host Interface Symbol Type Parameter VIH1 VIL1 IIL1 IU1 VT+2 VT-2 IIL2 IU2 VOH1 VOL1 IOH1 IOL1 VOH2 VOL2 IOH2 IOL2 IOH2 IOL2 VOH6 VOL6 IOH6 IOL6 IOH6 IOL6 IDD1,2 IDD1,2 ISP ISP O6 Output Current for DASP# pin Output Current for DASP# pin Output Current for DASP# pin Output Current for DASP# pin PWR Power supply current (TA = 0C to +70C) PWR Power supply current (TA = -40C to +85C) PWR Sleep/Standby/Idle current (TA = 0C to +70C) PWR Sleep/Standby/Idle current (TA = -40C to +85C) -3 12 50 100 100 200 -3 8 O2 Output Current Output Current Output Current Output Current Output Voltage for DASP# pin 2.4 0.4 mA mA mA mA mA mA A A -8 8 -6 6 O1 I1 I1Z I1U Input Voltage Input Leakage Current Input Pull-Up Current Input Voltage Schmitt Trigger 0.8 Input Leakage Current Input Pull-Up Current Output Voltage Output Current Output Current Output Voltage 2.4 0.4 mA mA mA mA V -10 -110 2.4 0.4 -4 4 mA mA V 10 -1 uA uA V Min 2.0V 0.8V -10 -110 10 -1 2.0 uA uA V Max Units Conditions V VDDQ=VDDQ Max VDDQ=VDDQ Min VIN = GND to VDDQ, VDDQ = VDDQ Max VOUT = GND, VDDQ = VDDQ Max VDDQ=VDDQ Max VDDQ=VDDQ Min VIN = GND to VDDQ, VDDQ = VDDQ Max VOUT = GND, VDDQ = VDDQ Max IOH1=IOH1 Min IOL1=IOL1 Max VDDQ=VDDQ Min VDDQ=VDDQ Min IOH2=IOH2 Min IOL2=IOL2 Max VDDQ=3.135V-3.465V VDDQ=3.135V-3.465V VDDQ=4.5V-5.5V VDDQ=4.5V-5.5V IOH6=IOH6 Min IOL6=IOL6 Max VDDQ=3.135V-3.465V VDDQ=3.135V-3.465V VDDQ=4.5V-5.5V VDDQ=4.5V-5.5V VDD=VDD Max; VDDQ=VDDQ Max VDD=VDD Max; VDDQ=VDDQ Max VDD=VDD Max; VDDQ=VDDQ Max VDD=VDD Max; VDDQ=VDDQ Max T12-8.0 1241 I2 I2Z I2U 1. Sequential data transfer for 1 sector read data from host interface and write data to media. 2. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 66 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 12.2 AC Characteristics VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 1241 F02.0 AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <10 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 12-1: AC Input/Output Reference Waveforms 12.2.1 Host Side Interface I/O Input (Read) Timing Specification TABLE 12-9: Host Side Interface I/O Read Timing Symbol TSU (IORD#) TH (IORD#) TW (IORD#) TSUA (IORD#) THA (IORD#) Parameter Data Setup before IORD# Data Hold following IORD# IORD# Width Time Address Setup before IORD# Address Hold following IORD# Min 20 5 70 25 10 Max 20 20 Units ns ns ns ns ns ns ns T12-9.0 1241 TDF IOCS16#(ADR) IOCS16# Delay Falling from Address TDR IOCS16#(ADR) IOCS16# Delay Rising from Address Note: The maximum load on IOCS16# is 1 LSTTL with 50pF total load. All AC specifications are guaranteed by design. Valid Address1 TSUA (IORD#) IORD# TSU (IORD#) IOCS16# TDF IOCS16#(ADR) D15-D0 DOUT 1241 F03.0 TW (IORD#) THA (IORD#) TDR IOCS16#(ADR) TH (IORD#) 1. Valid Address consists of signals CS1FX#, CS3FX# and A2-A0. FIGURE 12-2: Host Side Interface I/O Read Timing Diagram S71241-04-000 12/06 (c)2006 Silicon Storage Technology, Inc. 67 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 12.2.2 Host Side Interface I/O Output (Write) Timing Specification TABLE 12-10: Host Side Interface I/O Write Timing Specification Symbol TSU (IOWR#) TH (IOWR#) TW (IOWR#) TSUA (IOWR#) THA (IOWR#) TDF IOCS16#(ADR) TDR IOCS16#(ADR) Parameter Data Setup before IOWR# Data Hold following IOWR# IOWR# Width Time Address Setup before IOWR# Address Hold following IOWR# IOCS16# Delay Falling from Address IOCS16# Delay Rising from Address Min 20 10 70 25 10 Max 20 20 Units ns ns ns ns ns ns ns T12-10.0 1241 Note: The maximum load on IOCS16# is 1 LSTTL with 50pF total load. All AC specifications are guaranteed by design. Valid Address1 TSUA (IOWR#) TW (IOWR#) IOWR# TDR IOCS16#(ADR) THA (IOWR#) IOCS16# TDF IOCS16#(ADR) D15-D0 TSU (IOWR#) DIN Valid 1241 F04.0 TH (IOWR#) 1. Valid Address consists of signals CS1FX#, CS3FX# and A2-A0. FIGURE 12-3: Host Side Interface I/O Write Timing Diagram (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 68 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 12.2.3 Multi-word DMA Data Transfer TABLE 12-11: Multi-word DMA Timing Parameters - Mode 2 Symbol T0 1 TD TE TF TG TH TI TJ TKR TKW TLR TLW TM TN TZ Parameter Cycle Time IORD#/IOWD# Asserted Pulse Width IORD# Data Access IORD# Data Hold IORD#/IOWD# Data Setup IOWD# Data Hold DMACK# to IORD#/IOWR# Setup IORD#/IOWD# to DMACK Hold IORD# Negated Pulse Width IOWD# Negated Pulse Width IORD# to DMARQ Delay IOWD# to DMARQ Delay CS(1:0) Valid to IORD#/IOWD# CS(1:0) Hold DMACK# to Read Data Released 25 10 25 5 20 10 0 5 25 25 35 35 Min 120 70 50 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns T12-11.0 1241 1. T0 is the minimum total cycle time, TD is the minimum IORD#/IOWD# assertion time, and TK (TKR or TKW, as appropriate) is the minimum IORD#/IOWD# negation time. A host should lengthen TD and/or TK to ensure that T0 is equal to the value reported in the device ID. Note: All AC specifications are guaranteed by design. CS1FX#/CS3FX# TM See note DMARQ See note DMACK# TI TD IORD#/IOWR TE Read DQ15-0 TG Write DQ15-0 TH 1241 F05.0 TF Note: The host should not assert DMACK# or negate both CS1FX# and CS3FX# until the assertion of DMARQ is detected. The maximum time from the assertion of DMARQ to the assertion of DMACK# or the negation of both CS0 and CS1 is not defined. FIGURE 12-4: Initiating a Multi-word DMA Data Transfer S71241-04-000 12/06 (c)2006 Silicon Storage Technology, Inc. 69 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet CS1FX#/CS3FX# T0 DMARQ DMACK# IORD#/IOWR TD TK TE TE Read DQ15-0 TG TF TH Write DQ15-0 1241 F06.0 TG TF TH FIGURE 12-5: Sustaining a Multi-word DMA Data Transfer CS1FX#/CS3FX# T0 DMARQ DMACK# IORD#/IOWR TE Read DQ15-0 TG TF TH Write DQ15-0 1241 F07.0 TN TL TK TD TJ TZ Note: To terminate the data burst, the Device shall negate DMARQ within the TL of the assertion of the current IORD# or IOWR# pulse. The last data word for the burst should be transferred by the negation of the current IORD# or IOWR# pulse. If all data for the command has not been transferred, the device shall reassert DMARQ again at any later time to resume the DMA operation. FIGURE 12-6: Device Terminates a Multi-word DMA Data Transfer (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 70 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet CS1FX#/CS3FX# T0 DMARQ DMACK# IORD#/IOWR TE Read DQ15-0 TG TF TH Write DQ15-0 1241 F08.0 TN TK TD TJ TZ Note: 1. To terminate the transmission of a data burst, the host should negate DMACK# within the specified time after a IORD# or IOWR# pulse. No further IORD# or IOWR# pulses shall be asserted for this burst. 2. If the device is able to continue the transfer of data, the device may leave DMARQ asserted and wait for the host to reassert DMACK# or may negate DMARQ at any time after detecting that DMACK# has been negated. FIGURE 12-7: Host Terminates a Multi-word DMA Data Transfer 12.2.4 Media Side Interface I/O Timing Specifications TABLE 12-12: SST55LD019A/B/C Timing Parameters Symbol TCLS TCLH TCS TCH TCHR TWP TWH TWC TALS TALH TDS TDH TRP TRR TREA TRC TREH TRHZ Parameter FCLE Setup Time FCLE Hold Time FCE# Setup Time FCE# Hold Time for Command/Data Write Cycle FCE# Hold Time for Sequential Read Last Cycle FWE# Pulse Width FWE# High Hold Time Write Cycle Time FALE Setup Time FALE Hold Time FAD[15:0] Setup Time FAD[15:0] Hold Time FRE# Pulse Width Ready to FRE# Low FRE# Data Setup Access Time Read Cycle Time FRE# High Hold Time FRE# High to Data Hi-Z Min 20 40 40 40 20 20 40 20 40 20 20 20 40 20 40 30 5 Max 40 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns T12-12.0 1241 Note: All AC specifications are guaranteed by design. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 71 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet TCLS FCLE TCS FCE# TWP FWE# TALS TALH FALE TDS FAD[15:0] or FAD[7:0] TDH TCH TCLH Command 1241 F09.0 FIGURE 12-8: Media Command Latch Cycle FCLE TWC FCE# TCS FWE# TALS FALE TDS TDH FAD[15:0] or FAD[7:0] ABYTE0 TDS TDH ABYTE1 TDS TDH ABYTE2 TDS TDH ABYTE3 TDS TDH ABYTE4 1241 F10.1 TWC TWC TWC TWP TWH TWP TWH TWP TWH TWP TWH TALH FIGURE 12-9: Media Address Latch Cycle (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 72 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet FCLE TCH FCE# TWC FALE FWE# TWP TDS FAD[15:0] or FAD[7:0] DIN 0 TWH TDH TWP TDS DIN 1 TDH TWP TDS DIN Final 1241 F11.1 TDH FIGURE 12-10: Media Data Loading Latch Cycle TRC FCE# TRES TRES TRP TRHZ DOUT 1 TCHR TRES FRE# FAD[15:0] or FAD[7:0] FRBYbsy# TREH TRHZ DOUT Final 1241 F12.1 DOUT 0 TRR FIGURE 12-11: Media Data Read Cycle (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 73 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 13.0 APPENDIX 13.1 Differences between SST's ATA Flash Disk Controller and ATA/ATAPI-5 Specifications 13.1.1 Idle Timer The Idle timer uses an incremental value of 5 ms, rather than the 5 sec minimum increment value specified in ATA specifications. 13.1.2 Recovery from Sleep Mode For ATA Flash Disk Controller devices, recovery from sleep mode is accomplished by simply issuing another command to the device. A hardware or software reset is not required. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 74 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 14.0 PRODUCT ORDERING INFORMATION SST 55 XX LD 019 A XX XXXX X - 45 - XXX -C-XTQW E XXX X Environmental Attribute E = non-Pb Package Modifier W = 100 leads or ball positions Package Type TQ = TQFP MV = VFBGA B = TFBGA Operation Temperature C = Commercial: 0C to +70C I = Industrial: -40C to +85C Frequency 45 = 45 MHz Version A/B/C Device Number 019 Voltage L = 3.3V Product Series ATA Flash Disk Controller 14.1 Valid Combinations Valid combinations for SST55LD019A SST55LD019A-45-C-TQWE SST55LD019A-45-I-TQWE SST55LD019A-45-C-BWE SST55LD019A-45-I-BWE SST55LD019A-45-C-MVWE SST55LD019A-45-I-MVWE Valid combinations for SST55LD019B SST55LD019B-45-C-TQWE SST55LD019B-45-I-TQWE SST55LD019B-45-C-BWE SST55LD019B-45-I-BWE SST55LD019B-45-C-MVWE SST55LD019B-45-I-MVWE Valid combinations for SST55LD019C SST55LD019C-45-C-TQWE SST55LD019C-45-I-TQWE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 75 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet 15.0 PACKAGING DIAGRAM TOP VIEW Pin #1 Identifier 0.17 0.27 14.00 BSC 16.00 BSC 0.50 BSC DETAIL .95 1.05 1.10 0.10 14.00 BSC .05 .15 16.00 BSC .09 .20 .45 .75 0- 7 1.00 nominal NOTE: 1. Complies with JEDEC publication 95 MS-026 variant AED dimensions although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 mm. 4. Package body dimensions do not include mold flash. Maximum allowable mold flash is 0.25 mm. 100-tqfp-TQW-0 FIGURE 15-1: 100-lead Thin Quad Flat Pack (TQFP) SST Package Code: TQW (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 76 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet TOP VIEW 6.00 0.08 10 9 8 7 6 5 4 3 2 1 ABCDEFGHJK A1 CORNER BOTTOM VIEW 4.50 0.50 10 9 8 7 6 5 4 3 2 1 KJHGFEDCBA A1 INDICATOR 0.32 0.05 (85X) 6.00 0.08 4.50 0.50 DETAIL 0.86 0.10 SIDE VIEW 1mm 0.075 SEATING PLANE 0.20 0.06 Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-225, this specific package is not registered 2. All linear dimensions are in millimeters 3. Coplanarity: 0.075 mm 4. Ball opening size is 0.29 mm ( 0.05 mm) 85-vfbga-MVW-6x6-32mic-0.6 FIGURE 15-2: 85-ball Very-Thin, Fine-Pitch, Ball Grid Array (VFBGA) SST Package Code: MVW (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 77 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet TOP VIEW 9.0 0.1 BOTTOM VIEW 7.2 0.8 10 9 8 7 6 5 4 3 2 1 ABCDEFGHJK A1 CORNER KJHGFEDCBA A1 CORNER 0.8 9.0 0.1 7.2 10 9 8 7 6 5 4 3 2 1 0.45 0.05 (84X) SIDE VIEW 1.1 0.1 0.12 SEATING PLANE 0.35 0.05 1mm Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.12 mm 84-tfbga-BW-9x9-450mic-2 4. Ball opening size is 0.38 mm ( 0.05 mm) FIGURE 15-3: 84-ball Thin, Fine-pitch, Ball Grid Array (TFBGA) SST Package Code: BW (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 78 ATA Flash Disk Controller SST55LD019A / SST55LD019B / SST55LD019C Data Sheet TABLE 15-1: Revision History Number 00 01 Description Date Jun 2003 Aug 2003 * * * * * * * * * * * * * * * * S71241(01): Initial release of the fact sheet (Advance Information) S71241(01): Fact sheet changes 2003/2004 ECU Data Book Revised BGA package to 84-balls (out of 100 positions) Reorganized the pin assignments for the BGA package - see Figure 3-2 on page 9 S71241(01): Fact sheet synchronized to and integrated into full data sheet S71241: Initial release of the data sheet (Advance Information) Updated the package outline for the BGA package Added the I/O Type column in Table 3-1 on page 10 Updated applicable tables and diagrams to reflect removal of TQP package and addition of MVW package. Migrated document to a Data Sheet. Made minor changes to section "Electrical Specifications" on page 63. Made minor changes to Figures 3-2 and 3-3 on page 8. Updated Table 4-1 on page 14. Applied new formatting. Updated Product Description. Updated VDD and VDDQ in Table 12-2 on page 63 02 Apr 2004 03 Mar 2006 04 * Dec 2006 Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com (c)2006 Silicon Storage Technology, Inc. S71241-04-000 12/06 79 |
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